İşe Almak için Binary Analysis Experts

  • İkili (Binary) Analiz
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  • traveller90 adlı kullanıcıyı işe alın
    1.7
    1 değerlendirme saatlik $15 USD
    Five years experience in Filemaker. Below are the area that i cover: -system architecture (tables linking design, complex attributes calculation between tables, files, etc). -report structure (normal, sub summary, report out of report with finite or infinite looping, etc). -customized excel report (using plugin, from...
    Five years experience in Filemaker. Below are the area that i cover: -system architecture (tables linking design, complex attributes calculation between tables, files, etc). -report structure (normal, sub summary, report out of report with finite or infinite looping, etc). -customized excel report (using plugin, from normal excel report up to super complicated report such as pivot, predefined formula between sheet, designing excel template etc). -filemaker server structure/setup/handling/maintaining etc. -familiar with the different between an offline vs hosting database (how to build a structure of system). -familiar with the different between Filemaker and Filemaker Webdirect (i have face and solved almost all webdirect limitations such as excel report, script trigger on object modify etc). Also i have experienced in creating a component database system, CRM, timesheet, calender, etc. I familiar with Filemaker 12, 13, 14, 15 and 16. Also with Filemaker server 12, 13, 15 and 16. daha az
  • loi09dt1 adlı kullanıcıyı işe alın
    1.6
    1 değerlendirme saatlik $50 USD
    A highly-skilled FPGA engineer with 6+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. An FPGA/Verilog/VHDL Codementor and Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus,...
    A highly-skilled FPGA engineer with 6+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. An FPGA/Verilog/VHDL Codementor and Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, VLSI/CMOS Design, Cadence ADE, /Virtuoso/Layout/Digital ASIC Design from RTL-GDSII. - Featured FPGA projects: + Video/Image Processing on FPGA: FPGA/Verilog/VHDL Implementation of Gesture Recognition, Fingerprint Identification, Image Compression in Wavelet Domain using DWT and SPIHT, Image Enhancements including Noise Filtering. + Fixed-point and Floating Point FPGA projects in Verilog/VHDL + AES, SHA 128, 192, 256 Implementations on FPGA + Single/Multicycle/Pipelined RISC/MIPS Processors in Verilog/VHDL/Logisim + Games on FPGA and many other projects daha az

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