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Computer architecture projects verilog İşleri:
| Proje/Yarışma | Tanım | Tekilfler/Girdiler | Beceriler | Başlangıç | Bitiş | Fiyat (EUR) | |
|---|---|---|---|---|---|---|---|
| Architecture Design | Freelance 3D artist(Interior/Exterior Designing) | 19 | İnşaat Mimarisi, 3B Tasarım | Apr 25, 2018 | Bugün6g 21s | €151 | |
| Architecture Condominium floorplan & 3D HD renderings | Please contact me | 40 | İnşaat Mimarisi, AutoCAD, 3ds Max | Apr 25, 2018 | Bugün6g 20s | €345 | |
| Verilog Code for Fast Fourier Transform | I am having difficulties in finishing my final year project. I would like to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not... | 11 | Mühendislik, Elektronik, Verilog / VHDL, Elektrik Mühendisliği, FPGA | Apr 25, 2018 | Bugün6g 16s | €125 | |
| Job oppourtunity for Graphic Design Engineer with Joulestowatts!! | Hi job seekers, EXP:5+ Notice period:Immediate to 30Days. Job Description: responsible for a new functional block of the complex 3D Graphics IP cores for a combined CPU/GPU development effort (APU and dGPU). RTL and DV skills are required. Knowledge of basic 3D pipelines Be part of a team of designers and verification engineers, working closely with other team members to implement and verify the... | 0 | C Programlama, Mikrodenetleyici, C++ Programlama, Montaj, x86/x64 Çevirici | Apr 25, 2018 | Bugün6g 13s | - | |
| Verilog coding | Verilog code of Simplified DES algorithm | 5 | Verilog / VHDL, Bilgisayar Güvenliği, Yazılım Mimarisi | Apr 25, 2018 | Bugün6g 4s | €12 | |
| bumglows architecture,basement,ground first & roof | These my project bumglows as a archetecture plan section elevation detail for section lighting & also plubring | 16 | AutoCAD | Apr 24, 2018 | Apr 24, 20185g 18s | €135 | |
| Convert a python program to vhdl | Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog. | 10 | Python, Verilog / VHDL, Yazılım Mimarisi, CUDA, Arduino | Apr 24, 2018 | Apr 24, 20185g 13s | €248 | |
| 3B Tasarım, İnşaat Mimarisi | Apr 24, 2018 | Apr 24, 20188g 10s | |||||
| Architecture Design | Create new front door / entrance , giving property more street appeal | 45 | İnşaat Mimarisi, 3B Tasarım | Apr 24, 2018 | Apr 24, 20185g 7s | €96 | |
| Modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) | I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using fou... | 5 | Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, Gömülü Yazılım, FPGA | Apr 23, 2018 | Apr 23, 20185g 2s | €149 | |
| Architecture Design | I specialize in 2D architectural drawing, both electrical and mechanical inclusive. | 15 | İnşaat Mimarisi, 3B Tasarım | Apr 23, 2018 | Apr 23, 20184g 13s | €303 | |
| Architecture project | Architecture project with virtual machine and finite state machine | 5 | C++ Programlama | Apr 22, 2018 | Apr 22, 20183g 20s | €22 | |
| Architecture Design | As built autocad drawings for an existing location in Oslo norway | 56 | İnşaat Mimarisi, 3B Tasarım | Apr 22, 2018 | Apr 22, 20183g 10s | €122 | |
| Architecture Design | urban design and landscape garden design plan any architectural design | 4 | İnşaat Mimarisi, 3B Tasarım | Apr 22, 2018 | Apr 22, 20183g 9s | €3525 | |
| MIPS Computer Design by Verilog HDL | I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL | 18 | Mühendislik, Verilog / VHDL, Montaj, Dijital Tasarım, FPGA | Apr 20, 2018 | Apr 20, 20181g 16s | €113 | |
| need to implement an ieee paper using verilog or vhdl. -- 2 | would like to get the implementation of given ieee paper using verilog/vhdl within 15 days | 10 | Verilog / VHDL | Apr 20, 2018 | Apr 20, 20181g 13s | €98 | |
| 200418_Verilog | All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours | 4 | Elektronik, Verilog / VHDL, Elektrik Mühendisliği | Apr 20, 2018 | Apr 20, 20181g 11s | - | |
| Architecture Visualization | Looking for an Experienced Unity Developer who have experience in Augmented reality and virtual reality is plus we want to develop apps for user visualize different apartment interior as well as exterior. who have suitable to fit this job please send me their apks and portfolio. | 40 | Mobile App Development, iPhone, C# Programlama, 3D Modelleme, Unity 3D | Apr 20, 2018 | Apr 20, 20181g 9s | €44 | |
| need to implement an ieee paper using verilog or vhdl. | would like to get the implementation of given ieee paper using verilog/vhdl within 15 days | 6 | Verilog / VHDL | Apr 20, 2018 | Apr 20, 20181g 9s | €319 | |
| Implementing Bit stuffing in verilog | Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's | 11 | Mühendislik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA | Apr 20, 2018 | Apr 20, 20181g 3s | €24 |
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