E1 framer verilog işler

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    2,497 e1 framer verilog iş bulundu, ücretlendirmeleri EUR

    We are building a prototype for a new kind of communication infrastructure. We have developed a new usability paradigm. The project is open source (GPL 3). We are looking for a skilled Framer designer (now Framer X), who nows well how to work with code components.

    €398 (Avg Bid)
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    16-point FFT Bitti left

    verilog code for radix-4 16 point fft

    €13 (Avg Bid)
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    My Website does not work anymore because of the old php version. I had 5.4 or 5.3. and strato does work starting from 5.6. The platform is X3M The mistake shown Call-time pass-by-reference has been removed in /mnt/web211/e1/99/51889299/htdocs/inc/ [URL'yi görüntülemek için giriş yapın] on line 3365 I need to fix the website that it would be shown

    PHP
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    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

    €15 (Avg Bid)
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    Please read all the details first. and I will create 45% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer...

    €10452 (Avg Bid)
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    Please read all the details first. and I will create 45% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer...

    €9311 (Avg Bid)
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    - Use the LTL WP CMS as a headless CMS for our JAMstack - Write a swagger doc with the exact api implementation - Write a wp plugin that builds your content according to this spec - Rebuild front end using gatsby (sprint by sprint) that consumes this api - Migrate necessary assets to S3 (plugin) - Deploy straight to AWS with Circle - Split-test versus Contentful and Netlify This is our current we...

    €493 (Avg Bid)
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    23 teklifler

    Please read all the details first. and I will create 40% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer...

    €811 - €818
    €811 - €818
    0 teklifler

    Please read all the details first. and I will create 40% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer...

    €798 - €799
    €798 - €799
    0 teklifler

    Please read all the details first. and I will create 40% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer...

    €798 - €798
    €798 - €798
    0 teklifler

    Please read all the details first. and I will create 40% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer...

    €812 (Avg Bid)
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    3 teklifler

    Please read all the details first. and I will create 40% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer...

    €665 - €798
    €665 - €798
    0 teklifler

    I have app design created in framer x. I need these app views converted to react native app. Design only in react native.

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    hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file

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    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

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    Verilog Expert Bitti left

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

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    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

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    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results should be demonstrated on MATLAB by comp...

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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €158 (Avg Bid)
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    7 teklifler

    Need help program FPGA with Artix-7 using Verliog.

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    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

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    Implement the Zen Protocol in the FPGA and update the Mining App

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    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions …)

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    Make a serial interface system using Verilog

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    I need a UI/UX designer to create prototypes for my website using Framer X. Let me know your experience with Framer X

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    I need a UI/UX designer to create prototypes for my website using Framer X. Let me know your experience with Framer X

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    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12

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    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12

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    Cisco voice gateway connection to SIP server and PSTN on E1 PRI

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    Javascript and Phraser framer work

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    Filming job in London (E1) for an accountants firm. Need approx 1 minute final footage of staff working at desks, having a meeting, moving around the office etc. Need a quote first. Final footage to be delivered in 1080 HD

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    We need some python software so to run as a service on on a linux box collecting data from an rfid antenna over seriel rs 232 and the commands are sendt and recived as hex The reading should be able to be configured as timed activation and as trigger The data has to be stored in a database sql maria ... Command examples Please check below hex commands : Open the serial port, (the read/write d...

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    Design of a signal generator using verilog hdl. Should be done using Vivado Design Suite . More details in chat.

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    I looking for source code game mobile Pls refer apk app this game [URL'yi görüntülemek için giriş yapın] [URL'yi görüntülemek için giriş yapın]

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    image watermarking baed on dct algorithm in verilog code, need to implement in xilinx board

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    Part 1: Dynamic Patterns Using LEDs Requirement In this part, you are required to write a Verilog code that produces at least four different dynamic patterns, that is changing with time with reasonable speed. And those patterns are controlled by switches. Features • Use the most left switches to change the patterns. • Design your own patterns. • Use reasonable speed, not too slow n...

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    An application with an interface for user to calculate the output of supplied events. T = Issue E1,E2, En ....is the event A, B,.... is the cause user should be given a choice to provide event, cause. For every event, it need can and must have have 2 input, which can be cause or event. when it is a event, then user will be prompt for 2 inputs, since the logic cannot stop at events. Then c...

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    Verilog game Bitti left

    I have a verilog game. I need a freelancer to change the resolution of the game and add a background.

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    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

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    I want to implement the Ethernet connection. The deliverables are as follows -Verilog code to run on a Spartan 6 Board - (xc6slx100) -simulation time diagrams (more details will be given to the winner) - The code should be able to transmit and receive data at 1000mbs.

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    Hi Behailu D., I noticed your profile and would like to offer you my project. We can discuss any details over chat. conversion python to verilog

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    El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su...

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    El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su...

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    Trophy icon Design Flyer in 24 hrs Bitti left

    I need a flyer designed in 24 hrs please ensure its of a nice size to post on social media especially instagram. details to include: Saturday 10th November 2018 at Track & Records 94 Middlesex St, London E1 7EZ Music Policy: RnB, Hip Hop, Dancehall, Reggae, Trap, Afrobeats, Garage & House Use T&R maybe as background Image or use the image in there some where. use my attach...

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    Garantili
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    54 girdi

    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be pixel by pixel but rather, it should keep s...

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    A calculator has to bee designed using System Verilog. It includes designing ALU, memory and system controller.

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