Fpga işler

My project is to transfer data between Hps and Fpga on altera De1 soc board. Fpga side there will be Sdram and from the hps we should be able to read and write the data. The data transfer will be done with through AXI bridges and this hardware part can be designed using Quartus 2 Qsys. Hps can be programmed using C language using altera de-5. Ultimate goal is to transferring data. I am new to this field and don't know exactly what to do. I have created Qsys part( with sdram controller, pll , hps i.e cyclone v , jtag uart) I have successfully created the connections with the master slave AXI Avalon interface. Now don't know how to proceed further.

I want a video in which you have to show that how we connect a FPGA from the Xilinx software . you have to show the complete process for connect the FPGA from the Xilinx software .

Build a filter on FPGA

Need to work on Altera De1-Soc board. Need to make communication between HPS and FPGA. Software used are Quartus 2 Qsys.

lsb based steganography algorithn implenting in fpga with and withou pipelining

I would like to have a PCB layout design for a small circuit with FPGA and Memory. The schematics are available in Altium designer project.

Please see the attached file for an idea of the project.

FPGA

FPGA

We are looking for experienced PCB layout designer to work on a Xilinx Artix 7 FPGA embedded system board. System description: * Xilin Artix 7 FPGA based embedded system. * QSPI Flash, NO DDR * Multiple power modules, including 12V to 45V boost converter * One high speed digital LVDS connected peripherals * other SPI and I2C peripherals, like ADC, temp sensor etc. Job descriptions: * Schematic ready and compiled * Components footprints ready * Mechanical constrains ready * Space critical * board size < 5cm * 5cm * 10 layer or less Requirement: * Previous Xilinx FPGA embedded system PCB layout experience * Experience of BGA fan out * Experience of high speed digital differential signal layout and matching * Experience of high voltage boost c...

I need a Model of OFDM Tx RX designed in System generator FPGA the designer know about system generator software.

I want complete solution for Serial Communication Interface, between PC and my custom FPGA board.

I have an ADC chip 'EV10AQ190' and I want to interface it with Virtex-6 FPGA '6VLX240TFF1156'. The task is to simply acquire the analoge data using FPGA and display it on PC.

Using ailtera DE1 SOC board trying to transfer data from HPS to FPGA through OpenCL software used- Quartus ii The objective is to transfer the data back and forth on DE1 SOC board.

64 chs DAQ, FPGA, 16 bits resolution, 40dB gain (PGA), 20MHz sampling frequency, noise figure 2nV/Sqrt(Hz), ref. voltage Vref=1 volt Vpp, USB connection to PC for data acquisition. Suppose I have 64 sensors which give time dependent data and those data need to acquire simultaneously.

Development of FPGA firmware for data acquisition of high-speed ADC modules and transmitting the data via PCIe The aim of the project is to design and implement a modular FPGA firmware for multi-channel data acquisition, the configured depending on the connected ADC on "Partial Reconfiguration" the FPGA interfaces for data acquisition and transfers the data to the processing via PCIe to an embedded computer. The firmware is used in a new modular measuring system. The modular measurement system has 5 slots, which are provided for the insertion of ADC boards. The slots have a direct connection to the FPGA I / O banks.

The aim of the project is to design and implement a modular FPGA firmware for multi-channel data acquisition, the configured depending on the connected ADC on "Partial Reconfiguration" the FPGA interfaces for data acquisition. skbiswas[at][iith][ac][i] 64 Chs,16 bit system, 60dB gain, noise figure 1nV/sqrt(Hz)

Using ailtera DE1 SOC board trying to transfer data from HPS to FPGA through OpenCL software used- Quartus ii The objective is to transfer the data back and forth on DE1 SOC board.

I have an Altera DE0 board, we need to read analog signal and generate two streams of output: DAC to audio and PWM to motor control. Then the frequencies of the output signals need to be plotted on LCD screen to see visual image of the two data streams. Beginner-intermediate level work, need project at earliest so priority given to those who have necessary equipment to begin work.

A PCB based on the Xilinx FPGA Artix 7 is under development. Remote programming is required and is posible using the Xilinx QuickBoot method for FPGA Design Remote Update. Details on the attached file

Need to implement a 20 in and 20 out switch on an FPGA with slave I2C port. This device will be controlled by a master via 400kHz I2C. In & out Signals will be 3.3V and < 50kHz range. Please recommend a device to put it on.

Job description<br />Job Description: Creates emulation/Field Programmable Gate Array (FPGA) models from a Register Transfer Level (RTL) design using emulation/FPGA synthesis, partitioning and routing tools. Defines and documents RTL changes required for emulation/FPGA. Develops hardware and software collaterals and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation pla...

I requiere someone that could read the specs for Xilinx’s FPGA XC7A35T-1FTG256C and recommend where to connect a 500 MHz DAC and a 500 MHz ADC with LVDS interfaces using the IOSERDES modules within the FPGA. Aditional information on the attached specs file

project name : Implementation of OFDM on FPGA with mixed radix 8-2 algorithm using verilog. I want full blocks and input and output waveform also.

This is the project that i done in my final year of Btech. Project is based on the implementation of bpsk modulator and demodulator on spartan 3 fpga board.

Data Hiding Using Verilog

​Use HDL coder (with HDL verifier, fixed point designer etc.) to convert a Matlab function (kernel_em.m) to synthesisable fixed point HDL code using Simulink blocks.

steganography using vhdl on fpga

Project consists of FPGA which captures data on a main serial bus (SB1) and sends to an ARM controller running WinCE7. There is also redundant serial line (SB2) on which the same data is coming. If the main line does not receive data within 'x' seconds, data should be captured from redundant line. 'x' should be kept as variable which will be modified according to the requirements. The communication between FPGA and ARM controller is using UART at a baud rate of 921600 (SB3). Serial bus Protocol for SB1 (same for SB2) There will be a Bus Administrator & several devices on the SB1/SB2. The Bus Administrator communicates to the devices by issuing a Master frame and the devices send their response through slave frames. Data rate is 1.5Mbps & use...

i need an electrical engineer .who have knowledge of SVPWM in fpga with VHDL timeline 3 to 5 day

Job description: Solarflare FDK provided a complete "Tick to trade" example. It only works on 1 10G port. The FPGA card will keep receiving UDP packets from a server. When it received a interested packet, it sends out a TCP packet back to the server. The detail of this sample is on page 111 of the attached user guide. Modification: 1. 4 port mode We need to modify this example, such that it operates at 4x10G ports mode. The usage of port is as follow: Port 1 (10G): receive UDP packets from source 1 Port 2 (10G): receive UDP packets from source 2 Port 3 (10G): send out TCP packet if interested UDP packet is received Port 4 (10G): normal network card usage 2. trigger condition Modify the sample such that the trigger condition...

Job description: Solarflare FDK provided a complete "Tick to trade" example. It only works on 1 10G port. The FPGA card will keep receiving UDP packets from a server. When it received a interested packet, it sends out a TCP packet back to the server. The detail of this sample is on page 111 of the attached user guide. Modification: 1. 4 port mode We need to modify this example, such that it operates at 4x10G ports mode. The usage of port is as follow: Port 1 (10G): receive UDP packets from source 1 Port 2 (10G): receive UDP packets from source 2 Port 3 (10G): send out TCP packet if interested UDP packet is received Port 4 (10G): normal network card usage 2. trigger condition Modify the sample such that the trigger condition...

Device: Solarflare AOE card (SFA7942Q) description link : FPGA board: Altera Stratix V A7 Job description: Solarflare FDK provided a complete "Tick to trade" example. It only works on 1 10G port. The FPGA card will keep receiving UDP packets from a server. When it received a interested packet, it sends out a TCP packet back to the server. The detail of this sample is on page 111 of the attached user guide. Modification: 1. 4 port mode We need to modify this example, such that it operates at 4x10G ports mode. The usage of port is as follow: Port 1 (10G): receive UDP packets from source 1 Port 2 (10G): receive UDP packets from source 2 Port 3 (10G): send out TCP packet if interested UDP packet is received Port

Device: Solarflare AOE card (SFA7942Q) description link : FPGA board: Altera Stratix V A7 Job description: Solarflare FDK provided a complete "Tick to trade" example. It only works on 1 10G port. The FPGA card will keep receiving UDP packets from a server. When it received a interested packet, it sends out a TCP packet back to the server. The detail of this sample is on page 111 of the attached user guide. Modification: 1. 4 port mode We need to modify this example, such that it operates at 4x10G ports mode. The usage of port is as follow: Port 1 (10G): receive UDP packets from source 1 Port 2 (10G): receive UDP packets from source 2 Port 3 (10G): send out TCP packet if interested UDP packet is received Port 4 (10G): normal

Device: Solarflare AOE card (SFA7942Q) description link : FPGA board: Altera Stratix V A7 Job description: Solarflare FDK provided a complete "Tick to trade" example. It only works on 1 10G port. The FPGA card will keep receiving UDP packets from a server. When it received a interested packet, it sends out a TCP packet back to the server. The detail of this sample is on page 111 of the attached user guide. Modification: 1. 4 port mode We need to modify this example, such that it operates at 4x10G ports mode. The usage of port is as follow: Port 1 (10G): receive UDP packets from source 1 Port 2 (10G): receive UDP packets from source 2 Port 3 (10G): send out TCP packet if interested UDP packet is received Port 4 (10G): normal

produce project in Vivado/verilog for FPGA

We need FPGA programmer for one of our Gateways project

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Membuat spectrum analyzer pada fpga de1 menggunakan bahasa vhdl

Hi TechnocracyPune, I noticed your profile and would like to offer you my project. I have set the project ...offer you my project. I have set the project to $10.00 in case that you decide that you cannot work on this project. We can discuss any details over chat the details and see if you can help me. I am looking for a coder who can do the following: - Digital PID Controller for a servo motor, Loop rate of the PID controller is 100KHz or greater. - The Schematic design for such controller using a DSP, FPGA or a combination of both. - The digital module will need at least one DAC and two ADC's to sample the current of the motor and the signal position feedback of the motor. I would like to discuss a proposal on a document first and next the design. Let me know if you would l...

This is my MSc project. I have to implement on Wavelet Packet Transform and a support vector machine on FPGA. Our University has Altera Cyclone V SoC Dev kits which I want to use as demo board for my project. I have written and simulated MATLAB code for the deign which I can provide to the designer.

3 sinusoidal and symetrical phase with shifted 120 grade each............................................................................. thank you

3 sinusoidal and symetrical phase with shifted 120 grade each............................................................................. thank you

Development of FPGA firmware for data acquisition of high-speed ADC modules and transmitting the data via PCIe The aim of the project is to design and implement a modular FPGA firmware for multi-channel data acquisition, the configured depending on the connected ADC on "Partial Reconfiguration" the FPGA interfaces for data acquisition and transfers the data to the processing via PCIe to an embedded computer. The firmware is used in a new modular measuring system. The modular measurement system has 5 slots, which are provided for the insertion of ADC boards. The slots have a direct connection to the FPGA I / O banks.

Design a16-bit RISC MIPS Processor. Required - Approach, verilog code, test-benches, output wave form, constraints file and implementation on SPARTAN - 6 FPGA board

Based on the virtex 7 series FPGA complete a Gigabit Ethernet UDP transceiver, If you have application experience of it, please bid. Best Regards WoXing

Hi Maveriss, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Currently looking for a coder who can design and write the code for a PID type-controller loop for a servo motor using a DSP or DSP+FPGA combination.

Design a traffic light system where the north-south street has red, amber, green, and turn left green arrow lights and east-west street has only the red, amber and green lights. Amber, Green, and Green Left light should last 1, 3, and 2 time unit respectively. Left turning traffic will be allowed before the straight traffic. In the implementation on FPGA board use LEDs at E13, C14, C4, and A4 to represent North-South lights of Red, Amber, Green and Green Left Turn lights.