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    6,083 verilog ascii iş bulundu, ücretlendirmeleri EUR

    Windows Diğer ya da belirsiz Arduino uzerinden binaryi ascii ye ceviren kod

    €21 (Avg Bid)
    €21 Ortalama Teklif
    7 teklifler

    To whom it may concern, I'm looking for someone experienced who can develop a basic calculator using verilog on vivado with specific requirements in a short period of time. If you think this fits your skills, let me know and lets discuss things further!

    €20 (Avg Bid)
    €20 Ortalama Teklif
    6 teklifler
    Verilog on a weekend :) 5 gün left
    ONAYLI

    Hi, I have a couple of Verilog questions and would be happy to pay to pick someones brain! Attached is a simple HLS program that I synthesized to Verilog. I have some experience writing very basic Verilog programs, but some of the stuff would need an explanation. Attached is the Verilog project. And below in the text you will find the original HLS snippet. Ideally we would walk through the code an load the Verilog into Vivado and play a bit around with it for 2-3 hours while I ask a couple of questions. (1) CORDIC method is it applied here? (2) How does the entire program work? Honest question. (3) Why is there so much paramter overhead etc? (4) How would you simplify the application in Verilog? Requirements === (1) Happy to grab a Zoom or phon...

    €39 / hr (Avg Bid)
    €39 / hr Ortalama Teklif
    5 teklifler

    ...(Art. No. 0150-1324) - Arduino Mega 2560 R3 with RS232 shield Documentation of ASCII protocol: =========================== Goals: ====== 1. Finalize design and wiring for a control box employing - Arduino Mega 2560 with RS232 shield - push buttons, potentiometers, rotary encoders, status LEDs, digital displays 2. Write Arduino code making use of the E100-AT RS232 ASCII protocol to: - display operating states of E100-AT servo controller via status LEDs

    €735 (Avg Bid)
    €735 Ortalama Teklif
    20 teklifler
    Verilog programming-2 4 gün left
    ONAYLI

    Verilog programming project using Vivado. please bid if you can assist

    €35 - €47
    Mühürlü
    €35 - €47
    6 teklifler
    FPGA Project 4 gün left

    1 Verilog/VHDL Programming language 2 Understanding of the protocol and standards 3 FPGA knowledge & Programming hands on 4 Knowledge of the safety standards. Optical Data link 5 Networking concepts

    €336 (Avg Bid)
    €336 Ortalama Teklif
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    VERILOG code 4 gün left

    i need people who are very proficient in verilog, i will be giving few tricky question they need to help me

    €17 (Avg Bid)
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    2 teklifler

    Need help designing an adder architecture in Verilog/Systemverilog.

    €18 (Avg Bid)
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    6 teklifler
    €172 Ortalama Teklif
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    Verilog programming 2 gün left
    ONAYLI

    Verilog programming project using Vivado. please bid if you can assist

    €18 - €30
    Mühürlü
    €18 - €30
    5 teklifler

    Deadline is 25th Nov 2021 Please help and provide verilog code with the algorithm used to find cube root of fixed point 32 bit number and the out put should be 32 bit number with 16 decimal bits and 16 fractional bits. Also please write a description of algorithm used and about the architecture

    €62 (Avg Bid)
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    As a part of my PhD research, I need support from SAS programmer to handle ASCII/XML files. There are total 67 files. Each file contain different worbooks. I want to merge all workbooks and extract relevant data into excel sheet. Please call me at (Removed by Freelancer.com admin)

    €117 (Avg Bid)
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    need to extract the result for the verilog code regarding ASIC

    €122 (Avg Bid)
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    3 teklifler

    design a verilog block with the help of fsm logic

    €82 (Avg Bid)
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    7 teklifler

    Need an expert in VHDL and System Verilog

    €157 (Avg Bid)
    €157 Ortalama Teklif
    9 teklifler

    I have a project on implementing a 32-bit processor in VHDL or Verilog

    €56 (Avg Bid)
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    Neural network using System Verilog

    €158 (Avg Bid)
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    I developed a system that consists of 2 camera and 1 ethernet. The FPGA will get the image sensor data from 2 cameras and will process algorithm on the images. After processing, FPGA will send streaming data and processed data to the computer via Ethernet port. The protocol will be based on TCP/IP. I am looking for a long-term partner. I have many projects, so this will lead to other opportunities.

    €542 (Avg Bid)
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    Hello: We are looking for a powershell script that can communicate with (connect to) a monitor system via a serial port (i.e. COM1), issue ascii text commands asking the monitor to report back certain information, read the multi-line responses from each such request and write those responses to a text file. More specifically, a script that can do something like this: Open a configuration text file (i.e. C:LOsysScript) and read in the info for each variable…this file can look like this: SiteID:1234 ComPort:COM1 BaudRate:9600 Parity:Odd DataBits:7 StopBits:1 (The powershell script would reside in and be run from the same folder that contains the “” file… C:LOsysScript ) Variables read into the script from the config file could be “$SiteID&...

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    ...you finish one module. If you are new to Verilog, make sure your module is synthesizable before you move forward to next module. It's very easy that your code is un-synthesizable, if you are not familiar with verilog. If you synthesize everything together only at the end, and your code is not synthesizable. It's very possible that you need to re-write your code from scratch. Tutorial - Verilog You have to design several modules using Verilog, so you need to learn how to use this language. Many of you may have learned VHDL (another hardware description language) in the logic design course; you will find that Verilog is much simpler. Since Verilog is based on C, you will find it quite natural if you are familiar with C. Course material ...

    €405 (Avg Bid)
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    We need to build a software that can take values from user on PC and send it to the Arduino in ASCII format. The Arduino will then return some data in ASCII format; this data then needs to be plotted in excel

    €101 (Avg Bid)
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    I have a small task about differential amplifier... I need to implement a verilog-A code with assuming values of parameters ... with that code I have to get a symbol. From that I need to find some ac and DC and trans parameters I e., Offset , slew rate , rise time , fall time , 3dB, open loop gain etc., so what ever you are finding it should be initialize in code and we have to show on output side with same values in cadence environment.

    €4 / hr (Avg Bid)
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    I need help to implement a display controller using verilog/VHDL. I will share specfic details to the choosen freelancers.

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    I need help to implement a display controller using verilog/VHDL. I will share specfic details to the choosen freelancers.

    €44 / hr (Avg Bid)
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    I need microprocessor design in Logisim Need to expert electronic engineering and verilog microprocessor design

    €121 (Avg Bid)
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    Verilog Coding Bitti left

    See attached file.

    €129 (Avg Bid)
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    I need microprocessor design in Logisim Need to expert electronic engineering and verilog microprocessor design

    €163 (Avg Bid)
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    9 teklifler

    ...a 32 bytes with its associated decoder and multiplexer. The SRAM memory must have the following properties: 1- Addresses are from 0x8000 to 0x801F. 2- You can read and write one byte at a time. 3- The are special output signals that are required. They are listed in the table below. -------------- Requirement: Phase 1:Part 1: Verify the design using a logic design tool and an HDL tool (VHDL or Verilog) using structural method Part 2: List in a table the required components with their respective input and output labels. --- Phase 2: Part 3: Implement your design using Magic VLSI layout tool to generate your project layout Part 4: Test your design using irsim to simulate your project. phase 1 should be by Sunday Deliverables:

    €186 (Avg Bid)
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    Build a machine transliteration system that produce automatic text transliteration/conversion between two scripts/orthographies (using transliteration rules (direct orthographic mapping and dependency rules)). Transliterating from a Latin ASCII (non-diacritic) Charset (AC) to Latin Unicode (diacritic) Charset (UC) characters. The transliteration system should be able to automatically transliterate/convert texts written in AC characters to UC characters. For Example, the AC/ASCII word “Ingilish”, (English) is transliterated to UC/diacritic as “Æȋňğȋḽȋŝ”.

    €231 (Avg Bid)
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    Modify a existing controller on a FPGA (Cyclone III), which is used to calibrate the coefficients of a filter on another demo board. Already have a prototype, but needs to run modelsim and to modify existing verilog codes. Need someone who has a strong background with Quartus and FPGA design. Thank you.

    €169 (Avg Bid)
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    ı need help for microprocessor design who know assembly, Logisim ,Verilog and knowlage about FPGA

    €118 (Avg Bid)
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    Write a Verilog code for 8x233 multiplier . After that, run and simulate it in order to verify its correctness. Show wave forms. (preferably in MODELSIM)

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    I want to build alarm clock using vhdl in nexys4 ddr fpga board. Display clock in 7 segment display. Modify hour and minutes and set alarm and if possible set stopwatch. Not verilog. Using vhdl.

    €40 (Avg Bid)
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    Vhdl program to display digital clock using nexys 4 ddr in vga display. Vhdl not verilog. Using xilinx vivado

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    Need to implement TFET dual gate in Verilog-A

    €302 (Avg Bid)
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    ...that, given the following input returns normalized names, matching the results below: SELECT input_name, f_normalize_author(input_name) as normalized_name FROM author Andrea Perušić andrea perusic Adrian Suryo Mataram adrian suryo mataram Zhang Ping ping zhang Weinstock F f weinstock B Dorfman b dorfman I. Kosa-Somogyi i kosasomogyi 이영로 이영로 栗林 一彦 栗林 一彦 Note: - it converted "šić" to approximate ascii - it knew to reorder "Zhang" as a last name (based on common use?) - it guessed F is a first initial rather than the last name - it removed punctuation - it left Chinese, Korean, Russian etc characters untouched etc A sample of 1000 inputs and their expected outputs is attached. Upon successful completion of this project, you will provide: - sour...

    €34 / hr (Avg Bid)
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    ...create a fixed length output. Your task is to design a hash function! Choose two character strings that are between 5 and 15 characters long (including spaces). For example. "Julia 123" or "Password!". (a) (i) Design a function h whose input is a character string of any length and whose output is a (base 10) whole number. Your function must make non-trivial use of the ASCII values of each character. (For example, add all the ASCII values together – but don’t use this example!) (ii) Explain how your answer to (a)(i) satisfies the definition of a function. (b) Calculate the outputs of your function h for the two character strings you defined. (c) Choose a modulus m of between 4 and 12. Calculate the least residues modulo m of each of your two ...

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    We need someone who can implement count invocation on verilog. Further details will be shared with selected freelancers. Plz bid if you really know verilog otherwise dont waste our time. Thanks

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    I am developing a Android mobi...9f0c; byte[] binaryX = (); byte[] base64ble_out = (binaryX, ); Python code data = "56da65d63d4f15823d1bdb7ca293788d16c8906ee4dfc6975f957bdf38e3e02776562e81a54d9ee766a0891c18d7788db1a89f0c" # Standard Base64 Encoding sample_string_bytes = ("ascii") u64data = (sample_string_bytes) base64_string = ("ascii") print(base64_string) I am sure it's something really simple, but I just cannot get any code to work. I need some one to write ideally some Java and Python code to perform the conversion. I do not need any mobile app developing just the code to convert the incoming data via Base64 into the correct data string as above.

    €45 / hr (Avg Bid)
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    A partir del codigo de cisfrado, que facilito. Implementar el codigo para descifrado. Para ello se Implementará el algoritmo de descifrado y comprobarás su funcionamiento usando el mensaje cifrado como entrada y la clave operativa (MSBF). Si la simulación es correcta, el resultado será un bloque de 64 bits a cero (u ocho bytes a cero). A continuación, descrifrarás el mensaje cifrado que faciltaré con la clave operativa asociada. Y colocarás el mensaje en claro en la caja de texto de la tarea. Se proporcionará todos los archivos, claves en privado. Se necesita para el día 2 de Noviembre, es una tarea de estudios, fácil. El tiempo estimado de trabajo es 30 min porque el codigo de cisfrado lo tengo, solo es modif...

    €27 (Avg Bid)
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    I want to write the Verilog ( design & testbench) code of this FSM In the attached file

    €27 (Avg Bid)
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    I have code in verilog written need to generate report for this.

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    Verilog Expert needed with good hand's on FPGA

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    Need an expert in System Verilog

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    Build a character transliteration system (character converter) that transliterates from AC-to-UC characters. This system/converter should convert AC characters input or text/text-files to UC.

    €163 (Avg Bid)
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    Please read, understand and then respond. Experience with Sub-gigahertz SDR (Software Defined Radio) devices and computer-controlled radio devices such as the YARD Stick One required. Must be able to: • Work with RFCat firmware in UHF RFID frequency band, typically 860-960MHZ • Use YARDStick One to analyze, sniff communications between RFID reader and tags through its RFCat firmware. • Decode in ASCII, store and present the information that is sniffed between UHF reader and the UHF RFID tags. • Identify which specific tag(s) being read and source of UHF RFID messages, errors, status info, statistics and rough distance from sniffer. We have a system setup with RFID reader, 2 Yardsticks and several RFID tags (it is reading the communications as waveforms) that...

    €9253 (Avg Bid)
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    Need engineer with experience in MATLAB and VERILOG and can handle the project. More details will be shared over a chat

    €109 (Avg Bid)
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    Build a character transliteration system (character converter) that transliterates from AC-to-UC characters. This system/converter should convert AC characters input or text/text-files to UC.

    €16 / hr (Avg Bid)
    €16 / hr Ortalama Teklif
    8 teklifler

    Project need ethminer kernel(source and binary file) for xilinx u200. I want to program using vhdl/Verilog.

    €1330 - €2660
    €1330 - €2660
    0 teklifler

    I have done a Verilog module for clock and data recovery using DLL ( this is for simulation purposes only) I used Modelsim for simulation. In the transmitter (Tx), I only have a clock that has a random phase shift and random data both going to an XOR gate. The output is just data out. I also used Manchester coding scheme as a data format. The receiver (Rx) doesn't have a clock, it has to extract the clock and data using DLL. I would like to know what tools would help me to measure the phase shift (or jitter in the time domain)? I believe Simulink Matlab can do this but how to utilize my Verilog code? Is there any other software that is good in academia? I want to see which coding schemes (including Manchester, NRZ, RZ) that is more sensitive to jitter? I read that DLL is...

    €166 (Avg Bid)
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