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    4,988 verilog ascii iş bulundu, ücretlendirmeleri EUR

    CS 223 Digital Design: Smart Evacuation Elevator (System Verilog) Ödevin 21 Aralık 2018'e yetişmesi gerekiyor. Ödev hakkında bilgi için lütfen iletişime geçiniz.

    €132 (Avg Bid)
    €132 Ortalama Teklif
    3 teklifler

    Windows Diğer ya da belirsiz Arduino uzerinden binaryi ascii ye ceviren kod

    €21 (Avg Bid)
    €21 Ortalama Teklif
    7 teklifler

    ...implemented but the menu is still there so just a small fix I guess. 4) Sometimes the text displayed in the boxes after upload has strange characters - I think this is a unicode / ascii character support problem. Just the correct library etc may fix this. Again small thing. There should be weird characters. 5) Sometimes the text (if a lot) is outside the

    €12 - €23
    €12 - €23
    0 teklifler

    I want to do image processing for some of my images its basically a red color segmentation from the image and detect the patterns using verilog..... the image size is 240x240

    €245 (Avg Bid)
    €245 Ortalama Teklif
    7 teklifler

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    €176 (Avg Bid)
    €176 Ortalama Teklif
    1 teklifler

    This project need to implement the several LVDS interface between Xinix Atix and a sensor buffer This projec...content) This is the testing project, so that, you can get more projects after completing this. If you have experiences, you can complete within a few days. Deliverables: Verilog & buffer frame communication simulation in Xilinx Vivado

    €331 (Avg Bid)
    €331 Ortalama Teklif
    5 teklifler

    I need to develop a tool to convert EBCDIC format to ASCII. Freelancer with hands on experience in Mainframe and COBOL should easily able to do what is required..

    €114 (Avg Bid)
    €114 Ortalama Teklif
    7 teklifler

    The project goal is the implementation of a Verilog module to interface a high-speed ADC (250MSps) using DDR. The IO/delay shall be dynamically adjusted after reset thru a test pattern match using a test mode of the ADC. As part of the project a simulation test bench needs to be set-up to verify proper function of the interface.

    €1150 (Avg Bid)
    €1150 Ortalama Teklif
    15 teklifler

    Hi olegkaravaev84, I noticed your profile and would like to offer you my SystemVerilog/Verilog FP{GA project. We can discuss any details over chat.

    €396 / hr (Avg Bid)
    €396 / hr Ortalama Teklif
    1 teklifler

    an expert on FPGA and Verilog should bid only...

    €136 (Avg Bid)
    €136 Ortalama Teklif
    13 teklifler
    Verilog Design Bitti left

    I have one architecture, needs the RTL verilog code for the design to be made and followed by placement and routing to derive the power.

    €122 (Avg Bid)
    €122 Ortalama Teklif
    10 teklifler

    1. Vivado HLS fixed code optimization 2. Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HL... Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HLS 5. Intergration of IP generated in HLS in Verilog code

    €160 (Avg Bid)
    €160 Ortalama Teklif
    1 teklifler

    I can send you samples of the data and if you can convert them from the ASCII to a more readable format, you can have the job. Pays very well!

    €356 (Avg Bid)
    €356 Ortalama Teklif
    8 teklifler
    build mac unit Bitti left

    build mac unit using verilog language. I have already done the multypler part and I need help to build the rest

    €33 (Avg Bid)
    €33 Ortalama Teklif
    9 teklifler

    Basically I would like to have the verilog coding to build on my basys3 hardware. required to control the LED with left and right pushbutton within a range, to code different frequency for the LED within that range, to code one letter on each 7segment and the speed of the letter being displayed is depend on the frequency coded to the led. to code a

    €23 (Avg Bid)
    €23 Ortalama Teklif
    4 teklifler

    FPGA mining hardware - Xiling FPGA - Nexys Video - Can be leveraged from open source bitcoin miner code. - Based on Verilog. - Provide source code, constraints and full recipe for synthesis, implementation and bitstream generation - Connectivity via JTAG to the host (via USB). May consider UART instead, but as a less desirable solution. Mining software:

    €497 (Avg Bid)
    €497 Ortalama Teklif
    8 teklifler

    need a c# program to convert ascii text files to excel files with headings, an excel template will be provided

    €105 (Avg Bid)
    €105 Ortalama Teklif
    28 teklifler
    FPGA verilog Bitti left

    Using ModelSim or Quartus II for solving some problems i am working on

    €24 (Avg Bid)
    €24 Ortalama Teklif
    17 teklifler

    Simple but a little tedious. Type 1 page of old scanned computer code listing (PDF) into a text (TXT) format ASCII document accurately.

    €18 (Avg Bid)
    €18 Ortalama Teklif
    40 teklifler
    G code Sender Bitti left

    ...called bCNC and can be found here: [login to view URL] It is possible that much of the code can be used with an enhanced GUI. Communication with "grbl" is ascii characters over USB or from the UART of the Raspberry Pi to the Arduino UART. Mach3 is an older windows based application that operates a CNC machine by bit-banging the old

    €748 (Avg Bid)
    €748 Ortalama Teklif
    17 teklifler

    Code will contain encryption and decryption of elliptic curve cryptography

    €98 (Avg Bid)
    €98 Ortalama Teklif
    1 teklifler

    Hi, we have project for creating simple RISC processor through vhdl/Verilog. If interested will give more information

    €9 / hr (Avg Bid)
    €9 / hr Ortalama Teklif
    1 teklifler

    VHDL/Verilog basic RISC Processor, will give more details if interested

    €6 / hr (Avg Bid)
    €6 / hr Ortalama Teklif
    1 teklifler

    This project consists to port some c code (around 50 lines) to Verilog in order to run on a FPGA. Output of the contest Verilog .v source file equivalent of verilog.c testbench .v file equivalent to doSimulation() You can run the C code with "gcc main.c && ./[login to view URL]" Elements to select the winning bidder: - Partial screenshot of the implementation

    €59 (Avg Bid)
    €59 Ortalama Teklif
    8 teklifler

    ...long lines [root@65be04194cde wse-back]# file src/Demiurgo/Taobao/Items/Crawler/[login to view URL] src/Demiurgo/Taobao/Items/Crawler/[login to view URL]: HTML document, Non-ISO extended-ASCII text, with very long lines, with CRLF, LF line terminators...

    €23 (Avg Bid)
    €23 Ortalama Teklif
    3 teklifler

    ...with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x 32) 2- ALU 3- Instruction Register 4- Control Unit 5- PC register 6- Shift logic unit 7- Conditional logic unit 8- Three-level Cache for the Data

    €278 (Avg Bid)
    €278 Ortalama Teklif
    6 teklifler

    ...last-volume-open interest, will be forwarded into the Globalserver. B. Application interface also retrieves by entry missing intraday and daily data for a symbollist in plain ascii to fill gap. Intraday = 1-minute data (Date-Time-Open-High-Low-Close-Volume-Open Interest) Daily = format Date-Open-High-Low-Close-Volume-Open Interest Preferred is to retrieve

    €202 (Avg Bid)
    €202 Ortalama Teklif
    3 teklifler

    matrix multiplication using strassenalg and karatsuba alg and carry select adder

    €36 (Avg Bid)
    €36 Ortalama Teklif
    6 teklifler

    This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting

    €11 / hr (Avg Bid)
    €11 / hr Ortalama Teklif
    11 teklifler

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    €91 (Avg Bid)
    €91 Ortalama Teklif
    4 teklifler

    I am looking for a programmer who can develop a program that provides real-time conversion of 6 non-NMEA serial data (ascii/HEX/etc) to NMEA 0183 standard data. This program is to complement a Chartplotter on the same computer which only able to interface NMEA data. Looking for developer with skills and experience able to deliver within 1 month

    €1688 (Avg Bid)
    €1688 Ortalama Teklif
    16 teklifler

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

    €54 (Avg Bid)
    €54 Ortalama Teklif
    7 teklifler

    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [login to view URL] file.

    €25 (Avg Bid)
    €25 Ortalama Teklif
    9 teklifler

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €667 (Avg Bid)
    €667 Ortalama Teklif
    1 teklifler

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €166 - €498
    €166 - €498
    0 teklifler

    I have a code in Python that does the following NLP processes (using NLTK library): - Strips numbers, punctuation, non ASCII letters, etc. - Removes stop words and other given words - Runs PorterStemmer I need this converted into a C# script

    €193 (Avg Bid)
    €193 Ortalama Teklif
    12 teklifler

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €492 (Avg Bid)
    €492 Ortalama Teklif
    1 teklifler

    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

    €260 (Avg Bid)
    €260 Ortalama Teklif
    11 teklifler

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    €552 (Avg Bid)
    €552 Ortalama Teklif
    23 teklifler
    Vivado Expert Bitti left

    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

    €24 / hr (Avg Bid)
    €24 / hr Ortalama Teklif
    9 teklifler

    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

    €101 (Avg Bid)
    €101 Ortalama Teklif
    3 teklifler

    ...an input file ([login to view URL]) and print it onto the screen 3. Find the numerical ASCII value and print it on the screen 4. Change the letter to lowercase 5. Find the numerical ASCII value and print it on the screen 6. Change the letter to upper case 7. Find the numerical ASCII value and print it on the screen 8. Get an integer from an input file (input

    €18 (Avg Bid)
    €18 Ortalama Teklif
    7 teklifler

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    €1484 (Avg Bid)
    €1484 Ortalama Teklif
    8 teklifler

    ...and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture

    €1124 (Avg Bid)
    €1124 Ortalama Teklif
    13 teklifler

    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

    €95 (Avg Bid)
    €95 Ortalama Teklif
    6 teklifler

    ...if isinstance(bs[0], int): # Python 3 return list(bs) else: return [ord(c) for c in bs] def hex_to_bytes(hex): return binascii.a2b_hex([login to view URL]('ascii')) def decrypt_uri(e): n = int(e[2:10], 16) a = e[10 + n:] data = bytes_to_intlist(hex_to_bytes(e[10:10 + n])) key = bytes_to_intlist([login to view URL](

    €25 (Avg Bid)
    €25 Ortalama Teklif
    5 teklifler

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    €659 (Avg Bid)
    €659 Ortalama Teklif
    1 teklifler