Filtre

Son aramalarım
Şuna göre filtrele:
Bütçe
ile
ile
ile
Tür
Beceri
Diller
    İş Durumu
    1,543 verilog design iş bulundu, ücretlendirmeleri EUR

    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : Build a deep neural network using some of approximate MAC UNIT, *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in traini...

    €189 (Avg Bid)
    €189 Ortalama Teklif
    8 teklifler

    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : Build a deep neural network using some of approximate MAC UNIT, *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in traini...

    €145 (Avg Bid)
    €145 Ortalama Teklif
    11 teklifler

    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

    €30 / hr (Avg Bid)
    €30 / hr Ortalama Teklif
    1 teklifler

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

    €98 (Avg Bid)
    €98 Ortalama Teklif
    6 teklifler
    €174 Ortalama Teklif
    10 teklifler
    €74 Ortalama Teklif
    11 teklifler

    Complete few tasks on Verilog software

    €59 (Avg Bid)
    €59 Ortalama Teklif
    7 teklifler

    Hey looking for some help with some introductory logic building using Verilog code on the vivado software. Also Its for basys3. It’s really elementary and if you know how to use vivado this should be quick and easy money for you. Thanks

    €21 (Avg Bid)
    €21 Ortalama Teklif
    30 teklifler

    I need help in compiling a verilog code. I have already built a code that runs on a platform but when i run it on multisim, it gives me errors. I need an expert to guide me with this

    €11 (Avg Bid)
    €11 Ortalama Teklif
    4 teklifler

    I want to create a simple CPU the do some mathematics logic between two matrices using Verilog code

    €256 (Avg Bid)
    €256 Ortalama Teklif
    5 teklifler

    Hi, I need to emulate a crystal oscillator circuit (attached) based on wave digital filter (WDF). Basically we aim to have WDF emulation that match a Spice simulation (e.g. in Cadence). I Already have the circuit simulated in Cadence (the output attached) . Attached, my circuit (Crystal Oscillator) schematic that needs to be mapped to WDF along with its output waveform, you will notice that there ...

    €1010 (Avg Bid)
    €1010 Ortalama Teklif
    15 teklifler

    I have a task on verilog and i want someone who is experience on it to help me with it. Please bid only if you know youre an expert. I will share details with interested freelancer. Budget is limited, hiring will be on a weekly basis

    €22 (Avg Bid)
    €22 Ortalama Teklif
    3 teklifler

    Hi, I need a basic example of a state machine in VERILOG. We need to find the pattern "100" using machine states. We have 4 states: S0: Initial state S1: If 1 is found S2: If 0 is found S3: If 0 is found Encoding: S0: 00 S1: 01 S2: 11 S3: 10 Transition: Actual state / Input / Next state 00 - 0 - 00 00 - 1 - 01 01 - 0 - 11 01 - 1 - 01 11 - 0 - 10 11 - 1 - 01 10 - 0 - 00 10 - 1 - 01 T...

    €20 (Avg Bid)
    €20 Ortalama Teklif
    21 teklifler

    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

    €95 (Avg Bid)
    €95 Ortalama Teklif
    5 teklifler

    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

    €820 (Avg Bid)
    €820 Ortalama Teklif
    11 teklifler

    Needs to hire 3 Freelancers We are a small and growing company offering consulting and engineering services in many different areas of industry. Here you can find more about us: [URL'yi görüntülemek için giriş yapın] In order to enforce our team, we are seeking embedded systems designers with experience in the following domains: * PCB design (Altium Designer, Eagle, Ki...

    €503 (Avg Bid)
    €503 Ortalama Teklif
    69 teklifler

    Hi, I need : * ANN IN FPGA using my mac unit? *zybo-zynq-7000-arm-fpga-soc-trainer-board/ *verilog *MNIST

    €16 (Avg Bid)
    €16 Ortalama Teklif
    2 teklifler

    fix bug in verilog hdl for 8 bit

    €23 (Avg Bid)
    €23 Ortalama Teklif
    18 teklifler

    Design an 8-bit microprocessor using Verilog HDL by using Structural Verilog modelling. The individual components can be designed using behavioral modelling. Mandatory components: Instruction Memory Register File Data Memory ALU Control Unit Multiplexers Sign extend unit Program counter The Register File has two registers R0 and R1. Design the program counter and instruction memory such that input...

    €167 (Avg Bid)
    €167 Ortalama Teklif
    26 teklifler

    Enable all the listed hardware as the attached image. (2xMarvell ETH, MIG-DDR3, SD, QSPI Flash, PS-DDR3, uart) 2. Install Configured Petalinux, with Python, Flask, numpy, Pillow, littleCMS . Boot with QSPI (We will access this board on the Ethernet, make ETH0 DCHP and ETH1 Fixed @ [URL'yi görüntülemek için giriş yapın]) 3. Display JPEG/TIFF image file from SD in ...

    €419 (Avg Bid)
    €419 Ortalama Teklif
    9 teklifler

    I have the algorithm of what I want to implement, I just need help a second eye to help me understand how to implement it.

    €157 (Avg Bid)
    €157 Ortalama Teklif
    6 teklifler

    VLSI design for Reed Solomon FEC for 198,194 including documentation and explanation. Verilog files and simple testbench to prove the design. ASIC

    €107 (Avg Bid)
    €107 Ortalama Teklif
    10 teklifler

    I am looking for someone who can design a FPGA based hash algorithm including blake bmw sha512 skein luffa shavite simd echo hamsi shabal whirlpool and jh. Developer need to complete FPGA bitstream, and provide verilog source codes.

    €1161 (Avg Bid)
    €1161 Ortalama Teklif
    8 teklifler

    I want to implement a paper using verilog coding.. Kindly review paper before biding

    €23 (Avg Bid)
    €23 Ortalama Teklif
    5 teklifler

    Pipelined dual thread core processor design using system verilog, quartus software and altera development board. Please read pdf for detailed information.

    €151 (Avg Bid)
    €151 Ortalama Teklif
    5 teklifler
    Verilog Expert Bitti left

    Anyone who has hands on in verilog on An Accelerator-Based Video Display can help me

    €222 (Avg Bid)
    €222 Ortalama Teklif
    3 teklifler

    Anyone who is good in verilog and worked on Accelerator-Based Video Display can ping me

    €14 / hr (Avg Bid)
    €14 / hr Ortalama Teklif
    3 teklifler
    Verilog task Bitti left

    Anyone who has experience or worked on An Accelerator-Based Video Display using verilog can consult me.

    €17 (Avg Bid)
    €17 Ortalama Teklif
    2 teklifler

    Display image on the monitor using cyclone V fpga (tool quartus prime Lite edition) , i2c controller using qsys must be used to connect to hardware using verilog.

    €152 (Avg Bid)
    €152 Ortalama Teklif
    7 teklifler

    Technology research is already done. Internal FPGA system architecture is already designed. Therefore we only need you to implement and document it. Project is already split and documented as 10 milestones so that development can be done incrementally, step by step, and reviewed/monitored. Project is mostly Verilog development. Some simple programming necessary as well. Documentation is required...

    €14 / hr (Avg Bid)
    €14 / hr Ortalama Teklif
    20 teklifler

    We need a Verilog/VHDL developer to write some simple blocks for the Virtex-7 FPGA. The development environment is Xilinx Vivado. There are 5 blocks in total with the following functionalities: 1. CM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench. 2. RDM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and test...

    €449 (Avg Bid)
    €449 Ortalama Teklif
    12 teklifler

    In this project, you are required to develop a structural Floating-Point Unit (FPU) for use with a microprocessor. The processor needs to be capable of floating point addition and multiplication. The numbers are to be encoded into IEEE 754 single precision 32-bit format. The FPU should also be able to detect and flag the 'NaN' cases. For the project demonstration, interface the FPU to...

    €117 (Avg Bid)
    €117 Ortalama Teklif
    3 teklifler

    We are looking for an experienced FPGA developer to write technical documentation related to Xilinx and Verilog development as well as custom hardware accelerators. Content is in the form of educational papers for semi-technical audience. Each article/paper is expected to be around 1900 words (4-5 pages, plus custom diagrams/infographics). Candidates must be able to prove experience in RTL/Verilo...

    €118 (Avg Bid)
    €118 Ortalama Teklif
    12 teklifler

    I have 2 schemes. One with neuron and with genetic algorithm. I need to combine both to train this neuron via genetic algo. Using VHDL in ISE design suite 14.7. Here is [URL'yi görüntülemek için giriş yapın] picture of two symbols that I want to combine(gen - genetic algorithm with build in neuron process, neur4sigm - neuron with sigmoid func). I need to train this neur...

    €135 (Avg Bid)
    €135 Ortalama Teklif
    5 teklifler

    Write system verilog codes to build a dual thread core processor working using Tomasulo algorithm. Please view the attached PDF for detailed information.

    €107 (Avg Bid)
    €107 Ortalama Teklif
    7 teklifler

    Design Verilog 32 bit adder, and use that to implement multiply using Xilinx

    €91 (Avg Bid)
    €91 Ortalama Teklif
    2 teklifler

    I want the verilog UART code along with pin assignment, synthesis and waveform outputs using Quartus II tool on ALTERA DE2 Board.

    €43 (Avg Bid)
    €43 Ortalama Teklif
    3 teklifler

    Product suggestions for a high volume/high demand (tens of thousands to hundreds of thousands) FPGA based consumer product using A3P series FPGA from Microsemi. Product must be easy-intermediate difficulty to design Verilog/VHDL and final manufacturing cost in $30-$50 [URL'yi görüntülemek için giriş yapın] as little other electronic components as possible. There is a po...

    €99 (Avg Bid)
    Garantili
    €99
    8 girdi

    A project to implement a calculator(ALU) in Verilog code using Quartus program I need a detailed report with state diagram and finite state machine I need one who can access my computer to teach me how to do the settings of the program also the Verilog code will be implemented on ALTERA board(DE2-115) also I need instructions of how I can run on the board (its due Saturday sharp)

    €51 (Avg Bid)
    €51 Ortalama Teklif
    7 teklifler

    Microprocessor design project using system verilog in Modelsim and physical validation on Quartus Prime. I have started writing code for some of the blocks. The Register file, ALU and Instruction memory are nearly complete. Assistance needed in writing the remainder of the blocks: the instruction register, the micro controller unit, the W register, the program counter and anything else needed to w...

    €126 (Avg Bid)
    €126 Ortalama Teklif
    5 teklifler

    We are working on an FPGA based doppler flowmeter with a custom PCB. At the moment, we are in the process of modeling algorithms using raw data recording in Matlab. This freelancer will be tasked with coordinating with the DSP engineer to design and implement changes from the Matlab models into our custom PCB, which Cyclone IV based. There is an existing version of both the recording firmware and ...

    €157 (Avg Bid)
    €157 Ortalama Teklif
    9 teklifler

    Project requirements will be provided after talking.

    €220 (Avg Bid)
    €220 Ortalama Teklif
    3 teklifler

    I have a digital input measurement signal, 0 ~ 1.1V level. Each pulse is an event, that has a level HIGH width from 5ns to 10ns, and the minimum time between every 2 pulses' rising edges is 20ns. I need a system to histogram the time between all adjacent pulses' rising edges, that each bin of the histogram is 1ns wide. For example, starting from t=0, if the input signal has rising edge...

    €1027 (Avg Bid)
    €1027 Ortalama Teklif
    4 teklifler

    I need you to develop some software for me. I would like this software to be developed for Windows using Verilog/VHDL.

    €9 - €27
    €9 - €27
    0 teklifler

    Create verilog code for an Alarm clock with testbenches. Alarm clock will display on 7 segment display. More information available upon request. Simple Project

    €140 (Avg Bid)
    €140 Ortalama Teklif
    1 teklifler

    Hi, I need some help on a Altera FPGA testcase. A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO. Written in Quartus 18.1 with Verilog/System Verilog. And a testbench for verification. The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read enable from data bus (active low) a chip ...

    €180 (Avg Bid)
    €180 Ortalama Teklif
    5 teklifler

    I am enclosing description in the files.

    €34 / hr (Avg Bid)
    €34 / hr Ortalama Teklif
    4 teklifler

    Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.

    €26 (Avg Bid)
    €26 Ortalama Teklif
    6 teklifler

    Document with full requirements will be shared once discussed with person up for the job. Verilog code in top down design for a 4-bit ALU. A test bench will be needed to test design and needs to be able to program DE0-CV FPGA board to implement the full design.

    €89 (Avg Bid)
    €89 Ortalama Teklif
    11 teklifler

    Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.

    €140 (Avg Bid)
    €140 Ortalama Teklif
    2 teklifler