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Verilog project Freelancerları ya da İşleri mi Arıyorsunuz?

Verilog project konusunda yardıma mı ihtiyacınız var? Bugün bir freelancerı işe alın! Verilog project alanında uzman mısınız? Verilog project becerilerinizi kullanın ve bugün online para kazanmaya başlayın! Freelancer dünyadaki işler için en büyük pazardır. Şu anda üzerinde çalışmanızı bekleyen 17,764 iş var!

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Verilog project İşleri:

NO	Proje/Yarışma	Tanım	Tekilfler/Girdiler	Beceriler		Başlangıç		Bitiş	Fiyat (EUR)																					tip

Proje/Yarışma	Tanım	Tekilfler/Girdiler	Beceriler	Başlangıç	Bitiş	Fiyat (EUR)
15 hours of verilog work	I need you to develop some software for me related to XGMII. I would like this software to be developed in Verilog , 15 hours , 8 usd ph . =120 usd	3	Verilog / VHDL, Yazılım Mimarisi	Sep 18, 2017	Sep 18, 20174g 18s	€77
Real time 2-Dimensional FFT on FPGA using Verilog HDL	Please I wanna find some who can help me to finish this project as soon as possible, someone who is really expert with FPGA, Verilog HDL and Vivado.	20	Elektronik, Verilog / VHDL, Dijital Tasarım, FPGA, Programlama	Sep 14, 2017	Sep 14, 20171g 2s	€80
Functional Verification of SHA-1 algorithim using UVM	The Universal Verification Methodology (UVM) is a collection of API and proven verification guidelines written for system verilog to create an efiicient verification environment. UVM provides the best framework to achieve coverage-driven verification (CDV). CDV combines automatic test generation, self checking testbenches, and coverage metrics to significantly reduce the time spent on verifying de...	6	C Programlama, Verilog / VHDL, Mac OS, Elektrik Mühendisliği, Gömülü Yazılım	Sep 4, 2017	Sep 4, 2017Bitti	€129
10 hour work for 100 usd	10 G Ethernet project with Verilog	9	Verilog / VHDL	Sep 4, 2017	Sep 4, 2017Bitti	€120
I need a c and verilog developer	I have a small assignment which I need to finish and I hope that you can help me in that. In c I want someone who can explain me a pointer to an array and how to write to an array then read from it again. using malloc and those things. For Verilog, I need someone to help me complete some assignment on how to design 4 to 1 using two selections. The candidate should have at least a fast internet a...	8	C Programlama, Verilog / VHDL	Sep 4, 2017	Sep 4, 2017Bitti	€3
Real-time pulse compression radar waveform generation and digital matched filtering	I have added IEEE paper below. I need following three requirements. 1. project explanation. what is the plan to implement the paper. 2. Implement the paper in matlab. Need matlab simulations 3. Write a verilog code for the paper. Results has to match with matlab simulations.	7	Matlab ve Mathematica , Verilog / VHDL	Aug 29, 2017	Aug 29, 2017Bitti	€169
C project to generate a verilog file	I need you to develop some software for me. I would like this software to be developed for Windows using C or C++. 10 hour =100 usd	9	C Programlama, Yazılım Mimarisi, C++ Programlama	Aug 27, 2017	Aug 27, 2017Bitti	€85
			Elektrik Mühendisliği, Elektronik, Mühendislik, FPGA, Verilog / VHDL	Aug 27, 2017	Aug 27, 2017Bitti
Real time pulse compression radar waveform generation and digital matched filtering	I have added a paper to implement below. I need a person who will implement this paper in MATLAB and write a verilog code and simulate.	8	Matlab ve Mathematica , Verilog / VHDL	Aug 20, 2017	Aug 20, 2017Bitti	€129
c application to generate verilog file	Project: Sending out raw ethernet packet via 32 bit data path : Explanation: Writing a C application to generate the verilog file(.v) for XGMII 32 bit data and control path using pcap files. total = 100 USD ,which I expect to receive in a few days.	13	C Programlama, Verilog / VHDL	Aug 20, 2017	BugünBitti	€102
light to light conversion	Pv fed led lighting system: Harmony search algorithm based controller design I am using altium nano board . i need verilog code for above algorithm.	5	Verilog / VHDL	Aug 17, 2017	Aug 17, 2017Bitti	€122
Project for enggelectronics	Project: Sending out raw ethernet packet via 32 bit data path : Explanation: Writing a C application to generate the verilog file(.v) for XGMII 32 bit data and control path using pcap files. The first 8 byte of the first Ethernet frame in the pcap will be used for verilog generation. 1. I will give the pcap file , you will just take the first 8 bytes( 64 bits) of the pcap 2. Program...	1	C Programlama, Elektronik, Matlab ve Mathematica , Mikrodenetleyici, Gömülü Yazılım,	Aug 13, 2017	Aug 13, 2017Bitti	€50
Modify Altera FGPA Project and corresponding c library	We need a modification to an Ettus USRP SDR FPGA code. We have a working system and reference for a 1 TX and 1 RX system, using half of the USRP1, including the source files for the FPGA code and corresponding c library. We have working FGPA code for a 2 TX and 2 RX system, and but need about 15 lines of verilog code ported from the 1 TX and 1 RX system to the 2 TX and 2 RX system. Also, we nee...	16	C Programlama, Verilog / VHDL, FPGA	Aug 8, 2017	Aug 8, 2017Bitti	€996
pc connection to FPGA bye wiznet w5300	i am looking for the VHDL or Verilog code that have UDP or TCP protocol and can have Lan connection fpga spartan 6 to pc by wiznet W 5300 . anyone can help me for that?	4	Verilog / VHDL, FPGA	Aug 6, 2017	Aug 6, 2017Bitti	€65
HD Camera PCB Design and VHDL/Verilog project	Hi, The vision I have in mind is comparable to a machine vision camera. CMOSIS CMV2000/4000 cmos sensor will be readout over LVDS channels and acquired data compressed with H264 encoder (MPEG 4) and compressed data will be send over GigE and/or USB 3.0. I'm a PCB designer with RF design experience, for this project: 1. Propose design architecture ( Pure FPGA, FPGA+controller, DSP or SoC ...	6	Mühendislik, Verilog / VHDL, PCB Düzen, Ürün Tasarımı, FPGA	Aug 3, 2017	Aug 3, 2017Bitti	€2418
udp filtering based on udp data content, using verilog, zynq 7000 - open to bidding	(vinodluhar's) 10G sfp+ port will be read , using xilinx's free IPs , udp data will be filtered out, based on udp data content, and will be passed to other ethernet port, memory and ACP port of Zynq, using AXI interface with test bench for simulation.	9	Mikrodenetleyici, Elektrik Mühendisliği, PCB Düzen, Makine Öğrenimi, Ürün Tasarımı	Jul 18, 2017	Jul 18, 2017Bitti	€995
udp filtering based on udp data content, using verilog, zynq 7000	(vinodluhar's) 10G sfp+ port will be read , using xilinx's free IPs , udp data will be filtered out, based on udp data content, and will be passed to other ethernet port, memory and ACP port of Zynq, using AXI interface with test bench for simulation.	1	Mikrodenetleyici, Elektrik Mühendisliği, PCB Düzen, Makine Öğrenimi, Ürün Tasarımı,	Jul 18, 2017	Jul 18, 2017Bitti	€1041
Verilog question	I need help in a verilog question. I am a beginner in verilog so need some help.	16	Verilog / VHDL	Jul 16, 2017	Jul 16, 2017Bitti	€16
Small Verilog code	I need a small verilog code as soon as possible.	28	Verilog / VHDL, Dijital Tasarım, FPGA	Jul 15, 2017	Jul 15, 2017Bitti	€226
Training on Quartus verilog	Training using Verilog Altera-Quartus	1	Verilog / VHDL	Jul 15, 2017	Jul 15, 2017Bitti	€46