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Verilog project İşleri:
| Proje/Yarışma | Tanım | Tekilfler/Girdiler | Beceriler | Başlangıç | Bitiş | Fiyat (EUR) | |
|---|---|---|---|---|---|---|---|
| MIPS Computer Design by Verilog HDL | I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL | 17 | Mühendislik, Verilog / VHDL, Montaj, Dijital Tasarım, FPGA | Apr 20, 2018 | Apr 20, 20184g 6s | €110 | |
| need to implement an ieee paper using verilog or vhdl. -- 2 | would like to get the implementation of given ieee paper using verilog/vhdl within 15 days | 7 | Verilog / VHDL | Apr 20, 2018 | Apr 20, 20184g 3s | €101 | |
| 200418_Verilog | All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours | 4 | Elektronik, Verilog / VHDL, Elektrik Mühendisliği | Apr 20, 2018 | Apr 20, 20184g 1s | - | |
| need to implement an ieee paper using verilog or vhdl. | would like to get the implementation of given ieee paper using verilog/vhdl within 15 days | 6 | Verilog / VHDL | Apr 20, 2018 | Apr 20, 20183g 23s | €317 | |
| Implementing Bit stuffing in verilog | Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's | 9 | Mühendislik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA | Apr 20, 2018 | Apr 20, 20183g 17s | €25 | |
| Tcp sending on FPGA using verilog xgmii | Tcp sending on FPGA using verilog xgmii xilinx vivado | 5 | Verilog / VHDL | Apr 19, 2018 | Apr 19, 20183g 5s | €308 | |
| Sending and receiving tcpip xgmii packets over SFP+ | This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server. | 4 | Verilog / VHDL, FPGA | Apr 19, 2018 | Apr 19, 20183g 4s | €380 | |
| verilog expert only | more details will be given in the chat | 15 | Mühendislik, Elektronik, Verilog / VHDL, Elektrik Mühendisliği, FPGA | Apr 18, 2018 | Apr 18, 20181g 23s | €20 | |
| Traffic light controller | traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation) | 1 | Mühendislik, Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, | Apr 17, 2018 | Apr 17, 20184g 5s | €63 | |
| i need a verilog code for serial peripheral interface slave mode | verilog code for SPI slave module | 6 | C Programlama, Verilog / VHDL, Mikrodenetleyici, Yazılım Mimarisi, FPGA | Apr 10, 2018 | Apr 10, 2018Bitti | €29 | |
| Mips, Verilog project | Small project on computer architecture | 20 | Verilog / VHDL | Apr 9, 2018 | Apr 9, 2018Bitti | €17 | |
| Help to clear the error in vivado project, verilog code | I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated | 1 | Verilog / VHDL, Mikrodenetleyici, LabVIEW, Arduino, FPGA | Apr 7, 2018 | Apr 7, 2018Bitti | €11 | |
| ASIC design of a 16 core 16 bit microprocessor | I need the design of a microprocessor with 16 cores and 16 bit data bus with basic MIPS ISA, with 4 stage pipeline. I need the verilog code, testbench and physical design layout and testing (I will provide Synopsys tools) | 12 | Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA | Apr 6, 2018 | Apr 6, 2018Bitti | €463 | |
| Data flow from FPGA to PC over Ethernet (W5300 chip) | The task is to implement one direction data flow from FPGA to PC using: 1. Evaluation board Terasic DE0-CV ([url kaldırıldı, görüntülemek için giriş yapın]) and 2. wiz830mj ([url kaldırıldı, görüntülemek için giriş yapın]). The data should be sent to PC by TCP/IP protocol. The correct solution implies Verilog source code, which initializes W5300 ... | 1 | Verilog / VHDL, FPGA | Apr 2, 2018 | Apr 2, 2018Bitti | €91 | |
| Need an Verilog hardware description language expert | I need Verilog hardware description language expert. I need to modify two modules only: mips.v and mips-control.v. Details are in the attached file. | 7 | C Programlama, Verilog / VHDL, Mikrodenetleyici, Montaj, FPGA | Mar 30, 2018 | Mar 30, 2018Bitti | €89 | |
| MIPS and extend in Verilog | MIPS and extend in Verilog and datapath for a single-cycle | 4 | Java, Verilog / VHDL, C++ Programlama, Montaj, FPGA | Mar 30, 2018 | Mar 30, 2018Bitti | €87 | |
| Verilog HDL Project | Design a UART module to interface it with a PC | 20 | Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA | Mar 26, 2018 | Mar 26, 2018Bitti | €72 | |
| Digital Electronics | To create a real time audio effects machine using FPGA. It includes the following: 1.Real-time microphone-speaker system (capture voice from them PmodMIC3 and output at PmodAMP2). 2.Real-time delay in microphone-speaker system. [url kaldırıldı, görüntülemek için giriş yapın] Music Instrument. [url kaldırıldı, görüntülemek için giriş yapın] integrat... | 4 | Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, Arduino | Mar 26, 2018 | Mar 26, 2018Bitti | €15 | |
| generate square wave | I want to generate square wave by using verilog on Altera DE1-SoC and MTL2 with changing the frequency and Duty cycle | 1 | Mühendislik, Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, | Mar 25, 2018 | Mar 25, 2018Bitti | €38 | |
| VERILOG- FPGA Design Project | Create a real time audio effects machine. provided with a MEMs microphone to capture human voice and an audio amplifier to output your signal through earphones. This manual introduces you to the various concepts involved, and guides (not walks!) you through getting an audio FX machine up and running. Details given below | 8 | Mühendislik, Elektronik, Verilog / VHDL, Elektrik Mühendisliği, FPGA | Mar 25, 2018 | Mar 25, 2018Bitti | €77 |
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