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    1,355 verilog projects iş bulundu, ücretlendirmeleri EUR

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €243 (Avg Bid)
    €243 Ortalama Teklif
    11 teklifler

    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think t...any other sensors I haven't mentioned will work better? Therefore, I think we need some chat to find a solution before start working. FPGA: Xilinx Basys3 Language: Verilog HDL Software: Vivado 2015.4

    €156 (Avg Bid)
    €156 Ortalama Teklif
    6 teklifler

    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

    €136 (Avg Bid)
    €136 Ortalama Teklif
    16 teklifler

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    €105 (Avg Bid)
    €105 Ortalama Teklif
    10 teklifler
    200418_Verilog Bitti left
    ONAYLI

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    €43 - €69
    Mühürlü
    €43 - €69
    4 teklifler

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    €333 (Avg Bid)
    €333 Ortalama Teklif
    6 teklifler

    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

    €25 (Avg Bid)
    €25 Ortalama Teklif
    11 teklifler

    Tcp sending on FPGA using verilog xgmii xilinx vivado

    €352 (Avg Bid)
    €352 Ortalama Teklif
    4 teklifler

    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

    €358 (Avg Bid)
    €358 Ortalama Teklif
    5 teklifler

    more details will be given in the chat

    €21 (Avg Bid)
    €21 Ortalama Teklif
    15 teklifler

    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

    €66 (Avg Bid)
    €66 Ortalama Teklif
    1 teklifler
    Mips, Verilog project Bitti left
    ONAYLI

    Small project on computer architecture

    €18 (Avg Bid)
    €18 Ortalama Teklif
    20 teklifler

    I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated

    €11 (Avg Bid)
    €11 Ortalama Teklif
    1 teklifler

    I need the design of a microprocessor with 16 cores and 16 bit data bus with basic MIPS ISA, with 4 stage pipeline. I need the verilog code, testbench and physical design layout and testing (I will provide Synopsys tools)

    €486 (Avg Bid)
    €486 Ortalama Teklif
    12 teklifler

    ...Language=English&CategoryNo=167&No=921) and 2. wiz830mj ([login to view URL]). The data should be sent to PC by TCP/IP protocol. The correct solution implies Verilog source code, which initializes W5300 chip and sends some data to PC by TCP/IP. The solution should be verified by sending ascending numbers from 0 to 255(8 bits) in an endless

    €95 (Avg Bid)
    €95 Ortalama Teklif
    1 teklifler

    I need Verilog hardware description language expert. I need to modify two modules only: mips.v and mips-control.v. Details are in the attached file.

    €94 (Avg Bid)
    €94 Ortalama Teklif
    7 teklifler

    MIPS and extend in Verilog and datapath for a single-cycle

    €92 (Avg Bid)
    €92 Ortalama Teklif
    4 teklifler

    Design a UART module to interface it with a PC

    €76 (Avg Bid)
    €76 Ortalama Teklif
    20 teklifler

    To create a real time audio effects machine using FPGA. It includes the following: 1.Real-time micropho...PmodMIC3 and output at PmodAMP2). 2.Real-time delay in microphone-speaker system. [login to view URL] Music Instrument. [login to view URL] integration. [login to view URL] extra feature (open-ended). Verilog code will be given and it can edit according to the project.

    €14 (Avg Bid)
    €14 Ortalama Teklif
    3 teklifler