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    1,482 verilog projects iş bulundu, ücretlendirmeleri EUR

    Hi, I want a 2D convolution module in Verilog, using DSPs.

    €42 (Avg Bid)
    €42 Ortalama Teklif
    6 teklifler
    Quartus Bitti left

    I need you to develop some software for me. I would like this software to be developed for Linux . Edit the code in FPGA Board of a printer written in Verilog language.

    €24 (Avg Bid)
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    2 teklifler

    I need coding VERILOG code for BMI calculation that can be run in Quartus software and burn in ALTERA DE2 board. maximum 80usd

    €94 (Avg Bid)
    €94 Ortalama Teklif
    10 teklifler

    Need a serial multiplier coded in system verilog

    €110 (Avg Bid)
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    3 teklifler

    I have a serial adder that I need converted to serial multiplier in system Verilog. very easy only 1 hour work

    €19 (Avg Bid)
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    5 teklifler

    i need a code for serial multiplier using verilog not from online please

    €37 (Avg Bid)
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    12 teklifler

    Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...

    €95 (Avg Bid)
    €95 Ortalama Teklif
    10 teklifler

    i need a verilog code for serial multipler

    €27 (Avg Bid)
    €27 Ortalama Teklif
    8 teklifler

    Need help cleaning up some code, and matrix multiplication.

    €44 (Avg Bid)
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    6 teklifler

    I need Verilog Code for BMI calculation that can be running in Quartus software.

    €125 (Avg Bid)
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    2 teklifler

    I want someone to make a 40 minutes video to teach me how to Use cadence tool to synthesize digital circuit from Verilog code and simulation and do the static timing analysis and static power analysis in a given digital circuit which contains XORs and Multiplexers

    €34 (Avg Bid)
    €34 Ortalama Teklif
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    We require a simple oscilloscope project to be implemented using only Verilog code on DE1-SoC board by the latest date of 7th of May as agreed during the chat conversation. This project will comprise of modular Verilog code, fully commented, test-benches for verification and a technical report of the project. Altera Quartus software will be used for

    €186 (Avg Bid)
    €186 Ortalama Teklif
    1 teklifler

    A very simple oscilloscope developed using Verilog on Altera software, this project will be based on DE1-SoC Board and is expected to be concluded within a week. Only experienced FPGA engineers please.

    €194 (Avg Bid)
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    11 teklifler

    I want Verilog expert to help in some projects

    €71 (Avg Bid)
    €71 Ortalama Teklif
    1 teklifler

    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

    €69 (Avg Bid)
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    1 teklifler
    €20 Ortalama Teklif
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    ...to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not quite sure with the Verilog language

    €113 (Avg Bid)
    €113 Ortalama Teklif
    11 teklifler

    ...hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language,OVM/UVM Methodology knowledge and experience

    €307 (Avg Bid)
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    3 teklifler
    Verilog coding Bitti left

    Verilog code of Simplified DES algorithm

    €21 (Avg Bid)
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    9 teklifler

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €261 (Avg Bid)
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    9 teklifler

    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think t...any other sensors I haven't mentioned will work better? Therefore, I think we need some chat to find a solution before start working. FPGA: Xilinx Basys3 Language: Verilog HDL Software: Vivado 2015.4

    €149 (Avg Bid)
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    5 teklifler

    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

    €140 (Avg Bid)
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    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    €101 (Avg Bid)
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    200418_Verilog Bitti left
    ONAYLI

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    €44 - €71
    Mühürlü
    €44 - €71
    4 teklifler

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    €343 (Avg Bid)
    €343 Ortalama Teklif
    6 teklifler

    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

    €26 (Avg Bid)
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    Tcp sending on FPGA using verilog xgmii xilinx vivado

    €361 (Avg Bid)
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    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

    €368 (Avg Bid)
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    more details will be given in the chat

    €21 (Avg Bid)
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    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

    €68 (Avg Bid)
    €68 Ortalama Teklif
    1 teklifler

    Small project on computer architecture

    €19 (Avg Bid)
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    I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated

    €11 (Avg Bid)
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    I need the design of a microprocessor with 16 cores and 16 bit data bus with basic MIPS ISA, with 4 stage pipeline. I need the verilog code, testbench and physical design layout and testing (I will provide Synopsys tools)

    €500 (Avg Bid)
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    ...Language=English&CategoryNo=167&No=921) and 2. wiz830mj ([login to view URL]). The data should be sent to PC by TCP/IP protocol. The correct solution implies Verilog source code, which initializes W5300 chip and sends some data to PC by TCP/IP. The solution should be verified by sending ascending numbers from 0 to 255(8 bits) in an endless

    €98 (Avg Bid)
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    I need Verilog hardware description language expert. I need to modify two modules only: mips.v and mips-control.v. Details are in the attached file.

    €96 (Avg Bid)
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    7 teklifler

    MIPS and extend in Verilog and datapath for a single-cycle

    €95 (Avg Bid)
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    4 teklifler

    Design a UART module to interface it with a PC

    €72 (Avg Bid)
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    To create a real time audio effects machine using FPGA. It includes the following: 1.Real-time micropho...PmodMIC3 and output at PmodAMP2). 2.Real-time delay in microphone-speaker system. [login to view URL] Music Instrument. [login to view URL] integration. [login to view URL] extra feature (open-ended). Verilog code will be given and it can edit according to the project.

    €15 (Avg Bid)
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    3 teklifler

    I want to generate square wave by using verilog on Altera DE1-SoC and MTL2 with changing the frequency and Duty cycle

    €42 (Avg Bid)
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    1 teklifler

    Create a real time audio effects machine. provided with a MEMs microphone to capture human voice and an audio amplifier to output your signal through earphones. This manual introduces you to the various concepts involved, and guides (not walks!) you through getting an audio FX machine up and running. Details given below

    €83 (Avg Bid)
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    8 teklifler

    Write simple Verilog test bench for adder and multiplier.

    €57 (Avg Bid)
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    I am looking for a freelancer to help me with my project. The skill required is Verilog. Project is to write verilog code for digital alarm clock an will be simulating in Modelsim and will need testbenches as well. message me for more details

    €50 (Avg Bid)
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    Hi This...processor for face recognition. i this project i wrote verilog hdl coding and completed Ai algorithm for face recognition. so the next steps is to do the cross compilation of h.264 verilog coding with AI Algorithm. so iam expecting that to complete cross compilisation of h.264 verilog code with Ai algorithm. regards

    €95 (Avg Bid)
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    2 teklifler

    I have designed a UART which works fine and I need a testbench to verify it works perfectly.

    €23 (Avg Bid)
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    ...BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Pune. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience

    €6776 - €13551
    €6776 - €13551
    0 teklifler

    -This must be done on System Verilog NOT Verilog. -Need to be able to input random data and have results. -Need Explanation for every step taken and code written. (reason why you used the code and math -behind it) -Must have everything Required in the attachment. -Must be able to explain to someone with zero understanding of the topic This

    €137 (Avg Bid)
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    1 teklifler
    Adder tree Bitti left

    Parameterizable Verilog module that is calculating sum of N variables. It works in streaming mode and can used in convolution (FIR) and in phased array system.

    €34 / hr (Avg Bid)
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    1 teklifler

    I need someone expert in ASIC design to design digital clock with VERILOG CODE by Quartus software contact me for more details

    €108 (Avg Bid)
    €108 Ortalama Teklif
    9 teklifler

    Verilog modify processor design to add pipeline, based on MIPS processor. Existing verilog code provided and more details to be provided.

    €70 (Avg Bid)
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    4 teklifler