|Xilinx Trimode Ethernet MAC Project
||Create a project in Xilinx ISE that uses the OpenCores tri-mode MAC that works on the Xilinx SP605 Spartan 6 LX45 evaluation board. You can use one of the existing Xilinx demo projects as a base, or anything that allows the MAC/PHY to negotiate a 1Gbit and a 100Mbit connection and send and receive any sort of Ethernet packet (i.e. you don't need to choose an application that includes a Micro...
||Verilog / VHDL
||Sep 30, 2011
||Sep 30, 2011Bitti
||Elektronik, Verilog / VHDL
||Jul 11, 2011
||Jul 11, 2011Bitti
|Design an SPI interface for FPGA in Verilog or VHDL
||I have an Altera DE2-115 evaluation board with a Cyclone 4 FPGA processor (EP4CE115F29C7). I need a HDL design either written in Verilog or VHDL that implements a SPI core. I want to transfer data between the FPGA evaluation board and a PIC24 microprocessor evaluation board from Microchip. The data consists only of a few bytes that are transferred in both directions approximately every second.
||Elektronik, Mikrodenetleyici, Gömülü Yazılım
||May 23, 2011
||May 23, 2011Bitti
|Emulator on Verilog
||Roughly what you have to do is:
Write an emulator for the ARM machine. This should have a range of features to show the inner workings of the process of executing an assembly program.
Write a bubble sort program in ARM assembly. The start of this file is provided, you have to fill in the blanks.
Write an emulator that is able to read a ".emu" file in the format describ...
||Verilog / VHDL, Yazılım Mimarisi
||May 11, 2011
||May 11, 2011Bitti
|493438 Mastermind game in Verilog
||Here is a description of the project I'm needing, the first part (written plan of implementation) is due Tuesday morning. The final project is due May 10. It needs to be created using VERY basic Verilog code for use on an Altera DE2 board. Please email with questions.
"You are the design engineer and must create a working Mastermind game using the Altera DE2 board. You may
||PHP, Oyun Tasarımı, Her şey Kabul
||Apr 22, 2011
|ADC and ethernet on Xilinx Spartan 3 board
||I need a program to continuously capture the data from the ADC on the Spartan 3A or Spartan 3E board and stream it out over the ethernet on the board.
The 2 ADCs on the boards are 12/14 bits with a maximum sampling frequency of 1.5Msps so the ethernet communication must be configured for 100Mbs rather than 10Mbps.
For reference you can use:
[url kaldırıldı, görüntülemek i&cc...
||Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği
||Jan 5, 2011
||Jan 5, 2011Bitti
|convert Verilog to VHDL (part2)
||Convert a Verilog source code to VHDL
||Elektronik, Matlab ve Mathematica , Elektrik Mühendisliği
||Jan 2, 2011
||Jan 2, 2011Bitti
||PHP, Elektronik, Verilog / VHDL, Yazılım Mimarisi, Elektrik Mühendisliği
||Dec 26, 2010
||Dec 26, 2010Bitti
|Schematic diag &verilog code (using altera software ) 8hrs
||pls check the attachment for details
i want u to do this work very fast
i can pay 50$
pls use Altera software with small report of in ur own words
but deadline is very strict
[url kaldırıldı, görüntülemek için giriş yapın]
||Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, Gömülü Yazılım, PCB Düzen
||Dec 15, 2010
||Dec 15, 2010Bitti
|Digital System Design / Verilog Undergraduate Level Homework
||I am currently taking an undergraduate digtal systems design class and need some help doing a homework problem. This should be easy for anybody with basic HDL experience, or computer engineering graduates.
I have attached the scanned pages from our text book which contain the question that I need completed, which is question 16.
I have also attached an electronic version our textbook. Pl...
||Mühendislik, Yazılım Mimarisi, Yazılım Test Etme
||Dec 4, 2010
||Dec 4, 2010Bitti
|Digital System Design/Verilog Undergraduate Level Homework
||I am currently taking an undergraduate digtal systems design class and need some help doing the homework. This should be easy for anybody with basic HDL experience, or computer engineering graduates.
I have attached the scanned pages from our text book which contain the questions. You have to complete question 13 and 14. For each of them, you need to write the verilog code and simulate them ...
||Mühendislik, Elektronik, Yazılım Mimarisi, Yazılım Test Etme
||Nov 28, 2010
||Nov 28, 2010Bitti
|PID Controller in VHDL or Verilog
||Development of a PID controller in HDL (VHLD or Verilog) for Xilinx FPGA Spartan 6.
The development shall be with WEBPACK Xilinx.
The? implemented PID shall not be larger than 400 slices.
The The PID shall be developed? at 32bits precision, and intermendiate values extended at 48 bits and shall include:
• command ??" The setpoint, as commanded.
• feedback ??" as measur...
||Oct 17, 2010
||Oct 17, 2010Bitti
||Project: Ethernet Hub/Repeater on FPGA
Ethernet: 10/100 Base, Opencore IP
Connection: 2 IP Core + Host
Languages required: HDLs (Verilog, VHDL), HVLs (Tcl, Perl), C
Required skills: Ethernet, FPGA design
- If this work is successful, I have more project to work together.
- Compensation is based on your contribution.
We will work together, and I can handle all.
But, I may expect at ...
||Verilog / VHDL, Elektrik Mühendisliği
||Sep 26, 2010
||Sep 26, 2010Bitti
|Verilog/Modelsim Simple Pipeline
||This project is in Verilog and is 80% complete for a simple pipelined cpu. The are steps to be followed in the zip file to get the final correct wave form.
1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright rami...
||PHP, Mühendislik, Yazılım Mimarisi, Yazılım Test Etme
||Sep 7, 2010
||Sep 7, 2010Bitti
|ModelSim/Verilog Project for a simple pipelined CPU
||This project is in Verilog and is 80% complete for a simple multi cycle cpu. The code in comments needs to be uncommented and correct signals coded to complete the design. Further details are in the zip file.
||Windows Masaüstü, Proje Yönetimi, Mühendislik, Yazılım Mimarisi, Yazılım Test Etme, Microsoft
||Sep 7, 2010
||Sep 7, 2010Bitti
|FPGA verilog project
||Verilog design and testing skills
||Deneme / QA, Verilog / VHDL, Algoritma, C++ Programlama
||Sep 2, 2010
||Sep 2, 2010Bitti
||Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, Gömülü Yazılım
||Aug 26, 2010
||Aug 26, 2010Bitti
|Verilog: show me how to code this better
||I'm using an Altera CPLD device to decode an I2C communication path and control some GPIO lines. I've hacked up some code that's decoding the I2C lines, but I'm not very familiar with Verilog, so the implemention is messy. I want someone to look at my Verilog code and show me how it should have been written, making the I2C decoder it's own module, being able to write data ...
||Jul 30, 2010
||Jul 30, 2010Bitti
|designing using XILINX
||Assignement is due on thursday afternoon 5.00 pm australian time and its long and has to be done using XILINX and verilog
||Elektronik, Elektrik Mühendisliği
||May 25, 2010
||May 25, 2010Bitti
||Verilog / VHDL
||May 22, 2010