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    1,359 verilog projects iş bulundu, ücretlendirmeleri EUR

    Development of a PID controller in HDL (VHLD or Verilog) for Xilinx FPGA Spartan 6. The development shall be with WEBPACK Xilinx. The? implemented PID shall not be larger than 400 slices. The The PID shall be developed? at 32bits precision, and intermendiate values extended at 48 bits and shall include: • command ??" The setpoint, as commanded

    €478 (Avg Bid)
    €478 Ortalama Teklif
    5 teklifler

    Project: Ethernet Hub/Repeater on FPGA Ethernet: 10/100 Base, Opencore IP Connection: 2 IP Core + Host Languages required: HDLs (Verilog, VHDL), HVLs (Tcl, Perl), C Required skills: Ethernet, FPGA design - If this work is successful, I have more project to work together. - Compensation is based on your contribution. We will work together

    €2578 (Avg Bid)
    €2578 Ortalama Teklif
    9 teklifler

    This project is in Verilog and is 80% complete for a simple pipelined cpu. The are steps to be followed in the zip file to get the final correct wave form. ## Deliverables 1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party

    €26 - €4396
    €26 - €4396
    0 teklifler

    This project is in Verilog and is 80% complete for a simple multi cycle cpu. The code in comments needs to be uncommented and correct signals coded to complete the design. Further details are in the zip file.

    €26 - €4396
    €26 - €4396
    0 teklifler

    Verilog design and testing skills

    €1047 (Avg Bid)
    €1047 Ortalama Teklif
    15 teklifler

    ...I2C communication path and control some GPIO lines. I've hacked up some code that's decoding the I2C lines, but I'm not very familiar with Verilog, so the implemention is messy. I want someone to look at my Verilog code and show me how it should have been written, making the I2C decoder it's own module, being able to write data to several registers. The

    €75 (Avg Bid)
    €75 Ortalama Teklif
    1 teklifler

    Assignement is due on thursday afternoon 5.00 pm australian time and its long and has to be done using XILINX and verilog

    €191 (Avg Bid)
    €191 Ortalama Teklif
    4 teklifler
    VHDL Project Bitti left

    VHDL project Includes coding, initial report and final report. The board being used is: Altera® DE1 Development and Education board http...coding, initial report and final report. The board being used is: Altera® DE1 Development and Education board [login to view URL]

    €105 (Avg Bid)
    €105 Ortalama Teklif
    8 teklifler
    simulator Bitti left

    ...and subtract have latencies of 2 cycles, multiply has a latency of 10 and divide has a latency of 40 [login to view URL] be done using any high level language or HDL's like C, C++, verilog etc ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be

    €49 (Avg Bid)
    €49 Ortalama Teklif
    3 teklifler

    I am looking for someone to write verilog test benches for a project. All details are in the attached file ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables):

    €26 - €44
    €26 - €44
    0 teklifler

    Use VHDL-AMS or Verilog AMS to create a 4-bit DAC (switched capacitor). Should be able to take a 4-bit value from a .dat or .txt file (preferably, though can compromise and just have it as a variable in the code). The basic structure is 4 switches, 2 capacitors, and the switches are switched depending on the input so that the charge of Capacitor 1

    €26 - €4396
    €26 - €4396
    0 teklifler

    This project is to create a 2 port working switch in verilog which can be implemented on a fpga board like NetFPGA.

    €224 (Avg Bid)
    €224 Ortalama Teklif
    1 teklifler

    I have a website that needs to be tweaked constantly. The job is pretty much easy, but I plan on establishing a long term relationship with someone who has the skills I am looking for. It doesn't matter your experience level, just prove you can get the job done. For more details on the project, please goto the following website and watch a short video for precise instrustions. [login t...

    €2637 (Avg Bid)
    €2637 Ortalama Teklif
    1 teklifler

    Hi, I need to develop HDL editor with a) Verilog(HDL) syntax correction, b) with dynamic hints for good coding guidelines (as and when designer writes code, gets hints by editor for good coding rules). c) along with above functionality I need to have basic editor functionality like marking, copying, pasting, folding of code, etc. Also editor

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    0 teklifler

    Hi, I need to develop HDL editor with a) Verilog(HDL) syntax correction, b) with dynamic hints for good coding guidelines (as and when designer writes code, gets hints by editor for good coding rules). c) along with above functionality I need to have basic editor functionality like marking, copying, pasting, folding of code, etc. Also editor

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    N/A
    0 teklifler

    ...locations for setting control bits. Problem Statement: Part A In this part of the assignment, the delegate needs to identify the E12MUX architecture and model the E12MUX in Verilog. The FPGA being targeted should be considered and synthesizable code should be written targeting the efficient usage of chosen FPGA resources. The model should be simulated

    €225 (Avg Bid)
    €225 Ortalama Teklif
    9 teklifler