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    2,266 vhdl xilinx iş bulundu, ücretlendirmeleri EUR

    xilinx design suite ile single cycle mips işlemcisinin datapat ve kontrol bloklarının tasarımı ve belirtilen komutların icrasını gerçekleştiren bir [URL'yi görüntülemek için giriş yapın] vhdl dilinde yazılacaktır.

    €79 (Avg Bid)
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    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

    €30 / hr (Avg Bid)
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    I need vhdl code for signal processing. I need 256 point fir filter and 4096 point fft. create bid, many experience in signal processing. chatting discussing in detail

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    se trata de hacer unas practicas en la placa KCU105 de Xilinx utilizando el modulo AD9361 en simulink para exportar a código HDL para implementar en físico el sistema operativo de Windows

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    Need someone who has the PLDa PCIe ipcore license for Xilinx Vivado to help compile a FPGA project. I'll give you the source code. You compile and give me the bit file and compiled project.

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    The test program used for transmited data between DDR4 of FPGA and DDR4 of PC adopted windows 10 or win7 system via PCIe 3.0 x8. A tested result shows that the speed of PCIE3.0 *8 is over 7GB/s , which is tested by xilinx Kcu1500 FPGA board. However, the speed under win7 / win10 is only about 4.5-4.9GB/s. The minimum speed threshold should be 5.5 GB/s. And it will be helpful if the speed...

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    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

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    Scope includes the programing (vhdl) for the measurement and of AC voltage, currents, Power (active, reactive and apparent power) and Power Factor in FPGA (Spartan-6). Interfacing ADC and sensors with FPGA for current and voltage measurements. It also includes the display of measured parameter on LED display which is inbuilt on board). This is the brief requirement, interested people may contact ...

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    More details will be shared via chat

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    More details will be shared via chat

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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

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    Design and Document a VHDL Complex Mixer • Design should contain two 11-bit complex NCOs (Numerically Controlled Oscillator): • Assume clock freq of 100MHz • NCO #1: 11MHz • NCO #2: 18MHz • Design a complex multiplier component • Multiply the outputs of NCO #1 and #2 • Write the outputs of the NCOs and Complex Multiplier to a text file Theory of operation Detai...

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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. (I need to fix my code only) I don't want imaginary freelancer, please.

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    I need transmit data from DDR of Xilinx Kintex-7 to PC (windows 10 system). I would like to use PCIe 3.0 x8 to realize the project, But I found that the speed is not enough if I use the drive source code ordered by xilinx, which is only about 4.5-4.9GB/s. The minimum speed threshold should be 5GB/s. And I expect the speed is more that 6GB/s. Demands: 1) windows 10 system. 2) the speed is not l...

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    Have several ways to effectively reduce sidelobe the ACAR. In order to overcome the contradictions of weight-based processing techniques and ensure high resolution, I intend to use the NLFM signal. I want to do all the processing with one FPGA without using any other block like DDS. There is an expectation that a signal generator for NLFM signal with resolution of 2 ^ 32 and FIR code for correspon...

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    Have a design that is synthesizable and works properly on FPGA (nexys video - artix-7 based). The clock is set via clock wizard, and I need to make it flexible without the need to regenerate bistream every time. The dynamic clock setting can be done via "sw" pins (nexys video has 8 sw pins on board). When new clock frequency is set, the expectation that design will reset and restart oper...

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    Hi Jin :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the val...

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    Hi Nick :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the va...

    €27 (Avg Bid)
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    Hi Jin :) I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display..however my code is glitchy...if you could help me fix it it'd be a life...

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    Need to write VHDL program for Genesys 2 board for connecting a temperature sensor to xadc pin and display it in external LCD board

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    Handson training required on Xilinx Zc-702 including device programming in vhdl and its interfacing with perepherels like ADC, DAC, Memory etc.

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    I have problem in "fpga" I can't how to interface between power stage card and "fpga" card Can you write program in "vhdl" language?

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    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

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    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

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    Hi, We are looking for an experienced electronics engineer and software engineer, The project is to design a smart Home Cinema controller, the aim is to send data to a database, reading and writing data of different Video Projectors, Amplifiers, and many more devices via HDMI, USB, RS232, Ethernet, IR and many more. You will conceptualise the electronics and software for the system. We are stric...

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    Implemente un sistema de ecualización en tiempo real de tres bandas (bajos, medios y altos) en el FPGA de xilixn. Desarrolle los tres filtros necesarios para el ecualizador, los puede establecer en matlab o labview. Una vez definidos los coeficientes del filtro impleméntelos en el FPGA (a través de Matlab, Laview o Multisim). Se establece un bonus de 4 puntos para el grupo qu...

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    Build an FPGA Bitstream for Xilinx 420T PCI Card. Please contact for specific details.

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    We have developed Grostl RTL code for Grostl hash. We need an expert to optimize the code so I will use less LUT in Xilinx FPGA. We use Xilinx VCU9P and the goal of this project is to reduce the LUT down to 21%. The c code link is : [URL'yi görüntülemek için giriş yapın] The RTL code and spec. will be sent after the project is awarded. Target FPGA : Xilinx UltraScal...

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    Create a design with two counters and a 7-Segment Display • The first “Fast Counter” should count up 0 -> 49999999 and then reset to zero • When the Fast Counter reaches 49999999 it should output a single pulse on the “o_max_val” output to the second counter • The second counter (4-bit) counter should include a “i_count_enable” input, connected...

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    Implementation of Fractional order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please.

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    I need a simple VHDL program for measuring the time between two input signals. The VHDL program should be in structural code and should includes modules like Counter, BCDtoASCI, UART and FStateMachine + top level. I need also for every module and for the hole program testbenches.

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    Hey, I have working project in simulation that when I try to run it on board it doesn't work. I need someone with that board or that have familiar board to notice if there is problem with my code.

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    This includes the development of vhdl code for PWM generator, PID controller, flux estimator etc. Training would be web based on Skype or webex.

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    It is required to design a 4-bit binary divider. The division can be limited to un-signed numbers only. Feel free to implement the divider by any architecture you like, but be sure to understand and be able to verify the operation of the selected architecture. Fig. 1 shows a binary division example to recap the binary division process. -Structural and behavioral codes for the binary divider using...

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    I Have mips in VHDL code, I want to add to it UART

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    I got MIPS in VHDL, but when I run it on FPGA, It seems to do nothing, although it's working in simulation.

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    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [URL'yi görüntülemek için giriş yapın] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the tw...

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    Design a multifunction wristwatch that has time-keeping, alarm, and stopwatch functions. The wristwatch has three buttons (B1, B2, and B3) that are used to change the mode, set the time, set the alarm, start and stop the stopwatch, and so on. Pushing button B1 changes the mode from Time to Alarm to Stopwatch and back to Time. The functions of other buttons vary depending on the mode.

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    RTL design project All of the data required to explain what I want are found in the attached file

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    Dice game VHDL Bitti left

    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [URL'yi görüntülemek için giriş yapın] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the tw...

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    VHDL project Bitti left

    Anyone who is good in VHDL and can help me in implementing load, move, add, xor

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    Design a circuit that emulates an alarm system, which is armed and disarmed with a code consisting of 4 symbols given by the buttons on the board (for example btnC, btnL, btnR, btnU). The alarm is armed or disarmed when the correct code combination is entered. When the alarm is disarmed, LED0 is on, when the alarm is armed, LED15 is on. SW0 is a sensor, when the alarm is armed and SW0 = 1, the LED...

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    VHDL project Bitti left

    I need a vhdl project that integrates IoT and communications.

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    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [URL'yi görüntülemek için giriş yapın] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the tw...

    €71 (Avg Bid)
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    Technology research is already done. Internal FPGA system architecture is already designed. Therefore we only need you to implement and document it. Project is already split and documented as 10 milestones so that development can be done incrementally, step by step, and reviewed/monitored. Project is mostly Verilog development. Some simple programming necessary as well. Documentation is required...

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    I need single cycle 32 bit mips vhdl coding to find prime numbers. I will provide code to find prime number so you just have to build cpu for this specific purpose and I am also going to provide parameters for this architecture. I am gonna share project file after finalising with best person to do this job

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    We need a Verilog/VHDL developer to write some simple blocks for the Virtex-7 FPGA. The development environment is Xilinx Vivado. There are 5 blocks in total with the following functionalities: 1. CM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench. 2. RDM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and test...

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    I'm a electronic engineer and I have a good command on computer programs and also on digital programming like VHDL.

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    You have to write code and report for this .

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