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Proje/Yarışma Tanım Tekilfler/Girdiler Beceriler Başlangıç Bitiş Fiyat (EUR)
Trigger Design for FMCJESDADC1 Discuss with me to get more details on this task. Only person who has worked on FMCJESDADC1 should bid. 2 Verilog / VHDL, FPGA Dec 17, 2017 Bugün6g 12s €191
Simple Verilog code Write a simple verilog code to create dynamic lighting using led. see the attached files and respond 21 C Programlama, Verilog / VHDL, Mikrodenetleyici, LabVIEW, FPGA Dec 15, 2017 Dec 15, 20174g 5s €108
help me with modify some Verilog code know Verilog code, how how to use Quartus and FPGA board. 14 Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, LabVIEW, FPGA Dec 15, 2017 Dec 15, 20173g 20s €21
Create an ASIC board capable of hasing SHA256 (2-20Th/s) Good Day I am interested in finding somebody who will be able to design an ASIC board for my team and I. It needs to be able to hash SHA256 in order to mine bitcoin. It is up to you to decide whether you will be using FPGAs or other off-the-shelf ICCs. You will be working with some of the greatest experts in manufacturing and bussiness. It must meet or surpass the following specifications: ... 5 Elektronik, Mikrodenetleyici, Elektrik Mühendisliği, Devre Tasarımı, FPGA Dec 14, 2017 Dec 14, 20173g 11s €307372
Simulink to VHDL I have done a controller for a battery energy storage system using Matlab Simulink. I need to generate VHDL codes for my controller. If you have NOT done that, please do not wast my time. 5 Elektronik, Matlab ve Mathematica , Verilog / VHDL, Elektrik Mühendisliği, FPGA Dec 11, 2017 Dec 11, 20173s 28a €20
simulation/ VHDL Expert Needed -- Urgent job -- b I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 Mühendislik, Elektronik, Verilog / VHDL, Elektrik Mühendisliği, FPGA Dec 9, 2017 Dec 9, 2017Bitti €47
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 0 Mühendislik, Elektronik, Verilog / VHDL, Elektrik Mühendisliği, FPGA Dec 9, 2017 Dec 9, 2017Bitti -
DDR SD ram controller DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero 11 Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA Dec 8, 2017 Dec 8, 2017Bitti €379
FPGA Implementation of FIR filter 1. FIR design and simultion in Matlab. 2. Implement in FPGA(Xilinx Virtex-6 LX240T) and inter-connect with other logic blocks. 3. define registers for FIR filter and gain setting such that user can download filter co-efficients and gain settings through software to FPGA. 24 Matlab ve Mathematica , Verilog / VHDL, Elektrik Mühendisliği, FPGA Dec 7, 2017 Dec 7, 2017Bitti €667
Design of MIPS Datapath components Using Logisim Course: Computer Organization and Architecture Project: Design of MIPS Datapath components Using Logisim Objectives After completing this project you will: · Design a 32x 32 bit register file · Design a 32 bit arithmetic and logic unit (ALU) Register File The register file consists of 32 x 32-bit registers and has the following interface as shown in Figure 1: _ BusA and BusB... 10 Mühendislik, Elektronik, Verilog / VHDL, Devre Tasarımı, FPGA Dec 2, 2017 Dec 2, 2017Bitti €38
design and implementation of a MIPS CPU with Multi cycle Data path design and implementation of a MIPS CPU with Multi cycle Data path using the VHDL language 14 C Programlama, Verilog / VHDL, C++ Programlama, Montaj, FPGA Nov 30, 2017 Nov 30, 2017Bitti €133
bubble level project the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board. In the video attached in the .zip, the operation of the project 8 Verilog / VHDL, FPGA Nov 29, 2017 Nov 29, 2017Bitti €70
VHDL code for Pipe lined MIPS-RISC (5 stage) processor.(Code for Un-pipelined will be given) I need you to do pipelining for the MIPS-RISC (5 stage) Processor. I will give you the MIPS processor code, all you need to do is pipelining. I will upload the file once go through it. If you are interested, I will send you the code and question for which code has written.” Deadline is " Dec-03-2017 " 12 C Programlama, Mühendislik, Verilog / VHDL, FPGA, Paralel İşleme Nov 29, 2017 Nov 29, 2017Bitti €146
embedded s Project: The project consists of multiple phases. It is to develop a logic analyzer and waveform viewer (LA/WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single... 2 FPGA Nov 28, 2017 Nov 28, 2017Bitti €61
Network traffic processing using two FPGAs I want to get throughput and latency results of network traffic(Ethernet packets processing) using two FPGAs, while i have throughput and latency results of using one FPGA, so i want to compare both these results. The results of using two FPGA chips should be better than using one FPGA. 6 Mühendislik, Verilog / VHDL, Elektrik Mühendisliği, Ağ Yönetimi, FPGA Nov 26, 2017 Nov 26, 2017Bitti €573
SOC integration problem About timing violation at cross clock domain 1 FPGA Nov 26, 2017 Nov 26, 2017Bitti €21
System verilog - open to bidding I need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. Thanks 10 C Programlama, Verilog / VHDL, C# Programlama, C++ Programlama, FPGA Nov 23, 2017 Nov 23, 2017Bitti €9
single cycle 32bit mips verilog code -- 2 i need verilog code for 32bit mips single cycle it must contain instructions LW, SW, AND, ADD, ADDI, SUB, SLT, SLTI,b,BEQ, BNE, J, JAL and JR. and write a test-bench and stimulate and get the output waveform synthesis the code and submit to me 10 C Programlama, Verilog / VHDL, C++ Programlama, Montaj, FPGA Nov 23, 2017 Nov 23, 2017Bitti €8
System Verliog task available I need someone who can do task on system verilog. Deadline is 2 days. I want someone who can start now. More details will be provided to interested freelancer 8 Mühendislik, Matlab ve Mathematica , Verilog / VHDL, Elektrik Mühendisliği, FPGA Nov 22, 2017 Nov 22, 2017Bitti €20
Computer Design and ProtoTyping build a 32 bit architecture CPU, the CPU include the Register File, ALU, Control Unit, Instruction Register, Data Memory, PC Register, Shift logic unit, Conditional Logic Unit, and a 3-level cache read and write memory for the Data memory. The units need to be built in Verilog HDL then represented as a symbol on a schematic diagram and connected together using wires. Accompanied with each unit s... 8 Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA Nov 22, 2017 Nov 22, 2017Bitti €150
VHDL coding needed to be done by expert!! VHDL coding needed to be done by expert!! $30 CAD pay 8 Mühendislik, Elektronik, Verilog / VHDL, Elektrik Mühendisliği, FPGA Nov 22, 2017 Nov 22, 2017Bitti €19
LabWindows/CVI Project Simple Update.(send emails when yields goes down) - open to bidding I need a little update in my Test Program (Labwindows). All code and GUI and all is done, just need program be capable to send email automatically to specified people when yields goes down <97%. 4 C Programlama, Mühendislik, C# Programlama, Gömülü Yazılım, FPGA Nov 21, 2017 Nov 21, 2017Bitti €142
UVM verification of memory controller - open to bidding Need someone to verify a memory controller using UVM environment. CAN bus is used as a memory cycle initiator and write/read burst transactions need to be verified. 5 Perl, Verilog / VHDL, Kabuk Betiği, FPGA, Very-large-scale integration (VLSI) Nov 21, 2017 Nov 21, 2017Bitti €318
SMC Interface and SPI Slave Logic for CPLD Project 1) Implement high-speed 8-bit bus for MCU (ATSAM3U) to connect to Altera CPLD (5M160ZM68C5N) 2) Implement SPI Mode-0 SPI Slave in CPLD logic 3) Implement Dual SPI Slave mode in CPLD logic 4) Implement QUAD SPI Slave mode in CPLD logic 5) Implement general purpose I/O (8-bit) Port B in CPLD logic 6) Implement JTAG Host shift logic in CPLD logic 7 C Programlama, Elektronik, Verilog / VHDL, Mikrodenetleyici, FPGA Nov 21, 2017 Nov 21, 2017Bitti €24
Video transmission system and USB emulator Project for huge experienced engineers. Result: Altium project and firmware. Details of the project in the attachment. 4 Elektronik, Verilog / VHDL, PCB Düzen, FPGA Nov 20, 2017 Nov 20, 2017Bitti €1195
Differential Scan-attack and countermeasures on AES crypto-algorithm Hi, I wanted to implement research work on the AES(Advnaced Encryption Standard) algorithm and differential scan attack on the same to retriever secret key. In addition, the prevention mechanism against such attack has to be developed. Coding and simulation in verilog(Xilinix-ISE/Modelsim) will be fine. Also, requires documents for the implementation (step-by-step procedure), block diagram ... 8 Mühendislik, Verilog / VHDL, Elektrik Mühendisliği, Kriptografi, FPGA Nov 19, 2017 Nov 19, 2017Bitti €802
VHDL task URGENT Please check the attachment for the details Need to use Quartus ll 10 Mühendislik, Matlab ve Mathematica , Verilog / VHDL, Elektrik Mühendisliği, FPGA Nov 18, 2017 Nov 18, 2017Bitti €38
FPGA implementation of three phase locked loop i want to implement three phase locked loop implemented in simulink 20 Mühendislik, Matlab ve Mathematica , Verilog / VHDL, Elektrik Mühendisliği, FPGA Nov 18, 2017 BugünBitti €413
FPGA and DSP develper Looking for a developer to learn and implement a real time hardware implementation of spectrum analyzer upto 100mhz bandwidth using FPGA, fast ADCs and DACs. 16 Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA Nov 17, 2017 Nov 17, 2017Bitti €48
implement one project with system verilog in Zynq I need to implement the threshold block and verify that with two AXI VIP as you can see in the picture. I need a testbench which generates random numbers between 500 to 1000 and the threshold block count the number of data more than 500. the project can be done also with ILA but at this point I prefer system Verilog. Xilinx has a tesbecnh example which helps to write a code quickly. 4 Verilog / VHDL, Elektrik Mühendisliği, FPGA Nov 9, 2017 Nov 9, 2017Bitti €81
vhdl code using xilinx vhdl code using xilinx and simulate it using isim 14.7 7 Mühendislik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA Nov 7, 2017 Nov 7, 2017Bitti €27
embedded systems Modify the previous assignment so that, a bit string of 16 bits is sent from the UNO to the FPGA using a single data wire plus one or two control wires for synchronization (which could be either strobing or handshaking). When a pushbutton on the FPGA board is depressed and released, the FPGA sends a bit string of 16 bits to the UNO for display. Depending on the XOR result on the 16 bits, the ... 12 Verilog / VHDL, Elektrik Mühendisliği, FPGA Nov 7, 2017 Nov 7, 2017Bitti €157
FPGA Project Detail will be given in contact. 19 Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA Nov 7, 2017 Nov 7, 2017Bitti €147
Project for Pradeep S. Hi Pradeep S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 3 Python, Mikrodenetleyici, , Arduino, FPGA, Raspberry Pi Nov 1, 2017 Nov 1, 2017Bitti €14
Verification IP development for AXI Protocol using system Verilog VIP component development for AXI3.0 protocol with support for various features like burst type, burst size, protection, out of order, overlapping, aligned,WRAP,fixed burst . Develop BFM, Generator, Monitor, and Coverage models and also the slave model. 5 C Programlama, Verilog / VHDL, Yazılım Mimarisi, C++ Programlama, FPGA Oct 31, 2017 Oct 31, 2017Bitti €147
Electrocardiomiografo Integración de electrocardiografo y electromiografo haciendo uso de una FPGA para filtrado digital, procesamiento de datos y envío de información por medio de HC06 al celular. 9 Verilog / VHDL, Yazılım Mimarisi, Devre Tasarımı, FPGA Oct 30, 2017 Oct 30, 2017Bitti €45
Video product reviews We are a software company in the EDA industry. Our users are FPGA or ASIC engineers working in VHDL and/or SystemVerilog. We are looking for several people to create and distribute online video content for us on a regular basis. What skills do you need? - knowledge on hardware design projects - coding in VHDL and/or SystemVerilog - professional verbal and written English How can you ... 6 Elektronik, Video Servisleri, Verilog / VHDL, FPGA, Editorial Writing Oct 30, 2017 Oct 30, 2017Bitti €156
VHDL Coding VHDL Coding Project. Knowledge of Micro electronics is needed 12 Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA Oct 27, 2017 Oct 27, 2017Bitti €7
Digital system and microprocessor small task -- 2 small task on digital system and microprocessor using verilog amount usd 20 time 1 day 16 Elektronik, Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, FPGA Oct 22, 2017 Oct 22, 2017Bitti €25
Digital design using Verilog Use Basys 3 Board and Vivado 2016.2 I'll share the rest details 7 Verilog / VHDL, Mikrodenetleyici, Elektrik Mühendisliği, LabVIEW, FPGA Oct 20, 2017 Oct 20, 2017Bitti €36
verilog project making verilog on quartus II (cyclone IV) 12 Mühendislik, Verilog / VHDL, Yazılım Mimarisi, Montaj, FPGA Oct 18, 2017 Oct 18, 2017Bitti €125
veriloghdl code for calculation area THis must implement on quartus( altera FPGA cyclone IV) 3 C Programlama, Verilog / VHDL, Mikrodenetleyici, C++ Programlama, FPGA Oct 16, 2017 Oct 16, 2017Bitti €109
Simple Verilog Project Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3. 8 Mühendislik, Matlab ve Mathematica , Verilog / VHDL, Elektrik Mühendisliği, FPGA Oct 13, 2017 Oct 13, 2017Bitti €20
Color space conversions and FPGA's 3 pages report in two parts on: (i) fundamental information about FPGAs and their programming, and (ii) standard color spaces and formulas for converting those color spaces into other ones. (Plagarism free) finished in 3 days maximum. 9 Mühendislik, Verilog / VHDL, Elektrik Mühendisliği, FPGA Oct 13, 2017 Oct 13, 2017Bitti €56
VLSI PROJECTS FIND THE ATTACHED IEEE [url kaldırıldı, görüntülemek için giriş yapın] REQUIREMENTS 4 Verilog / VHDL, FPGA, Very-large-scale integration (VLSI) Oct 11, 2017 Oct 11, 2017Bitti €73
Linux, Elektrik Mühendisliği, Ubuntu, Debian, FPGA Oct 10, 2017 Oct 10, 2017Bitti
Metatrader, PLC & SCADA, Sonlu Eleman Analizi, Finansal Pazarlar, FPGA Oct 10, 2017 Oct 10, 2017Bitti
Assemble and calibrate audio amplifier Hello i am working in audio and develop a high end audio loudspeaker to power this loudspeaker i have chosen pcb amplifier i need a skilled person to get the whole working 1/ indicate me the power supply to use ( toroïdal) 2/do all the wiring (i provide the switch) 3/assemble the pcb board, toroidal transformer .... switch... it will happen in your city i already have switch... 6 Ses Servisleri, Mikrodenetleyici, PCB Düzen, Devre Tasarımı, FPGA Oct 8, 2017 Oct 8, 2017Bitti €186
STM32 motor control project template Hey guys, I started using STM32 motor workbench and FOC SDK v4.3, and the code is a bit more complex than what I'm used to. For that reason, I need someone experienced in STM32 FOC library, to create some functions that are easier to use for a part time coder. Project description as follows The target of this project is to design a template using STM32 FOC SDK v4.3. This template shall h... 12 Mikrodenetleyici, PLC & SCADA, Arduino, Devre Tasarımı, FPGA Oct 8, 2017 Oct 8, 2017Bitti €529
Audio File Processing in Matlab process audio file in Matlab, remove audio noise (Using a filter in Matlab). create a karaoke track from processed audio track and once the karaoke track is produced save the data back into an audio file. (Need Matlab Codes for this process. Audio File will be provided once contract awarded) 19 Ses Servisleri, Matlab ve Mathematica , Algoritma, Telekomünikasyon Mühendisliği, FPGA Oct 7, 2017 Oct 7, 2017Bitti €37
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