Need an Verilog hardware description language expert

$30-250 USD

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yaklaşık 6 yıl önce

$30-250 USD

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I need Verilog hardware description language expert. I need to modify two modules only: mips.v and mips-control.v. Details are in the attached file.

Proje No: 16592918

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7 teklif

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Son aktiviteden bu yana geçen zaman 6 yıl önce

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7 freelancers are bidding on average $109 USD for this job

@ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using Verilog please check my profile also please message me so that we can discuss more details best regards

$88 USD 1 gün içinde

5,0

(317 değerlendirme)

7,6

@hungfreelancer

I have 10 years of experience in the Asic design and verification. Please message me. Thank you

$50 USD 1 gün içinde

5,0

(2 değerlendirme)

1,7

@noblelabs

R&D division of Noble Labs consists of well experience industry persons and fresh and enthusiastic youngster. The mingle of experience and young people will give our clients very fast solutions. The youngsters are very energetic and stick to their course contents, so they build confidence in the company to try something new every day. Where the experience people will tell them how to do try what they want to try. This whole system will reduce the total time to market, and also the cost of the product.

$277 USD 4 gün içinde

0,0

(0 değerlendirme)

0,0

@umangangrish

Hi, I will provide u with after work support and the work will be on time. Relevant Skills and Experience I have experience in verilog design. This will be helpful in completing the project sooner.

$246 USD 3 gün içinde

0,0

(0 değerlendirme)

0,0

@EslamElGeddawy

Hi, I hope you are doing well and enjoying digital design.I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. I had the joy of building MIPS with further adjustments of my own about 2 years ago. As my graduation project, it was a very good experience, especially when our programs ran properly on an Altera Cyclone V FPGA in front of the examiners' committee. (you can take a look at it in my portfolio ) Throughout my 3 years of experience in the field, I had designed and implemented a part of LTE's physical layer right from the Matlab model, through RTL coding & simulations, till later back-end stages. To verify and test my projects, I usually simulated most of them using Verilog testbench and I used also UVM environments as well in verifying other projects such as for ALU and adder modules. I am really excited to return to work with MIPS and I would love to chat with you about your requirements and code. I wish you get the best out of this project. - Eslam

$45 USD 1 gün içinde