Sense-Amplifier-Based Flip-Flops for Timing in
Synchronous Digital Systems
Timing elements, latches and flip-flops (FFs, also known as registers) are critical elements of timing schemes in synchronous digital systems. The FF parameters in time domain that have to be optimized include setup time and clock-to-output delay, and the ability to absorb the clock skew. A class of registers featuring desired characteristics uses a sense-amplifier at the input and it is known as Sense-Amplifier-based Flip-Flops (SAFF). A thorough description of SAFF operation, as well as the modifications of the basic SAFF architecture are discussed in .
The ENSC853/462 Project involves a design of the improved Sense-Amplifier-Based Flip-Flop  in the 0.35 micron CMOS (cmosp35) technology. The schematic diagram of the SAFF is shown in Fig.1.
1) Design simulated and optimized SAFF circuit (Fig.1) using HSPICE and cmosp35 technology
2) Estimate the circuit performance through analysis of simulation results
3) Design the circuit layout using Cadence Virtuoso, followed by DRC and LVS (this task is optional).
 B. Nikolic, [url removed, login to view], [url removed, login to view], et. al., "Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements", IEEE Journ. Of Solid-State Circuits, vol. 36, No. 6, June 2000, pp. 876-884
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I have a [url removed, login to view] in electrical & communication engineering from Cairo university, I'm a [url removed, login to view] student in analog & digital circuit design & I may help in this project.