Sense-Amplifier-Based Flip-Flops for Timing in Synchronous Digital Systems

Sense-Amplifier-Based Flip-Flops for Timing in

Synchronous Digital Systems

Timing elements, latches and flip-flops (FFs, also known as registers) are critical elements of timing schemes in synchronous digital systems. The FF parameters in time domain that have to be optimized include setup time and clock-to-output delay, and the ability to absorb the clock skew. A class of registers featuring desired characteristics uses a sense-amplifier at the input and it is known as Sense-Amplifier-based Flip-Flops (SAFF). A thorough description of SAFF operation, as well as the modifications of the basic SAFF architecture are discussed in [1].

The ENSC853/462 Project involves a design of the improved Sense-Amplifier-Based Flip-Flop [1] in the 0.35 micron CMOS (cmosp35) technology. The schematic diagram of the SAFF is shown in Fig.1.

Project deliverables

1) Design simulated and optimized SAFF circuit (Fig.1) using HSPICE and cmosp35 technology

2) Estimate the circuit performance through analysis of simulation results

3) Design the circuit layout using Cadence Virtuoso, followed by DRC and LVS (this task is optional).


[1] B. Nikolic, [url removed, login to view], [url removed, login to view], et. al., "Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements", IEEE Journ. Of Solid-State Circuits, vol. 36, No. 6, June 2000, pp. 876-884

Beceriler: Dijital Tasarım

Daha fazlasını görün: virtuoso layout, systems analysis and design, schematic architecture, micron technology, digital domain, cmos layout, circuits design, cadence virtuoso layout, cadence design systems, cadence design, architecture schematic, vol, Systems analysis , sense, performance based, flop, flip, digital design, digital circuit design, design and simulation project, cmos design, circuit simulation, circuit analysis, basic circuit, schematic design layout

İşveren Hakkında:
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Proje NO: #6511362

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