Vivado Chirp Generator & FFT Integration fot Frequency detection

@Mahihassi

As an experienced Electrical Engineer with a Masters in Embedded Systems, my expertise perfectly aligns with your project requirements. I have a solid background in Digital Signal Processing and designing systems on FPGA, which makes me the ideal candidate for your FFT integration and Vivado Chirp Generator RTL design tasks. Throughout my career, I've honed my skills in VHDL/Verilog coding and using Xilinx IPs effectively. I propose to develop clean and optimized synthesizable VHDL/Verilog codes for the chirp oscillator that would be completely relevant to your specified 50-55 MHz sweep range. Furthermore, I have a seamless understanding of the Xilinx FFT IP, which will be crucial to connect and configure it to receive the chirp streams while ensuring accurate data-format conversions and steady hand-shaking. What sets me apart is not only my technical prowess but also my commitment to delivering reliable and foolproof solutions. In addition to providing a timing-compatible top-level design with constraints, I will also supply a self-checking testbench that simulates the chirp sweep, captures FFT output, identifies peak bins and dominant frequencies flawlessly. With me on your team, you can be confident of getting a clean transition across the band, correct moving peak detection without any artifacts or skipped samples in real time - both on simulation and actual FPGA.

@ducdctoandh

Hello, I’m interested in delivering the complete RTL-based chirp generation and FFT analysis system you described. I have extensive experience designing high-throughput DSP pipelines in Vivado, including DDS/NCOs, streaming FFTs, AXI-Stream integration, and hardware-verified testbenches. I deliver silicon-ready RTL, not just simulations. I have strong experience with DDS/chirp generation, Xilinx FFT IP (large-point, AXI-Stream), and fixed-point DSP, ensuring clean sweeps, correct framing, and stable FFT outputs. I work hardware-first, communicate clearly, and deliver verified, maintainable designs that scale easily to future projects.

@Netrapug

Hi, I want to introduce you my self as experienced freelancer with more than 8 years of experience in designing various digital circuits using VHDL/Verilog. My expertise is as follows 1. Strong in VHDL/Verilog coding 2. Expertise with FPGAs and Vivado 3. Verification of DUTs using VHDL/Verilog, BFMs 4. Experience in Signal processing like FFTs, Filters, Chirp Generators etc. 5. Experience with various communication protocols like SPI,I2C,UART, PCIe, LVDS, AXI etc. I feel I am very much suitable to execute this project because of my vast experience in Vivado tool and signal processing. Detailed Approach for the project. 1. writing functional equivalent MATLAB code for chirp generation 50-55 MHz, FFT and finding peaks/dominant frequencies 2. Hand-Written Synthesizable VHDL code for chirp generator using DDS/NCO, FFT IP and peak finding logic 3. Self checking testbench to validate the Top level VHDL module and Compare the VHDL outputs with MATLAB outputs at each stage i.e. Chirp generation output, FFT output and Peak findings 4. Once Functionally ok in Simulation, Write constraints for the targeted FPGA board 5. Synthesize, implement and generate bit file for programming FPGA. Lets hope for working together to complete the project. I promise that my deliverables will be in effective way to continue the work for long term collaboration. MESSAGE ME FOR FURTHER DISCUSSION AND CLARIFICATIONS OF GOALS/DELIVERABLES/TIMELINES

@nik016

Hello, For your Chirp/FFT project, while writing direct VHDL/verilog in vivado is an option a much better option is using Vitis HLS. I can write you the entire project in C error free and the AMD Vitis HLS will generate an optimized VHDL/Verilog code directly and it can be used right away in Vivado as an RTL code or IP package. Since it is in C, you can modify/change any parameter (e.g Chirp freq or FFT size, etc..) quickly in future yourself and re-generate the RTL code. Both fixed point and floating point options are also possible.

@yanatejaip5s

I got a lot experiences using Vivado as well as got background to do OFDM Baseband Processor. It also use FFT/IFFT block on TX and RX part. I contribute a lot RTL design modules from scratch.

@Mostafaihab1

Hi, I can implement this project and will be with you until you are fully satisfied with the results. Here is my approach: 1- Matlab/python modeling (as you wish but I prefer Matlab in mathematical computations): a "Golden Reference" model with bit-exact fixed-point precision, ensuring we know exactly how the hardware should behave before coding. 2- RTL coding: I will design a synthesizable, systemverilog parameterized DDS for the 50–55 MHz chirp, instantiate and configure the Xilinx FFT IP. 3- verification step: I will provide a self-checking systemverilog testbench that automatically compares the RTL simulation output against the MATLAB model to guarantee mathematical accuracy. 4- timing constraints and bitstream generation on vivado Waiting for your message/discussion if you're interested.

@syedfahadahmad33

Hello I just read out your description and am interested in your project. I am an Expert in FFT Integration and also did in the past. If you need Quality Work, then feel free to contact me Thanks

@ST0807

本人从事FPGA工作经验丰富，使用Xlince芯片包括K7系列 ZYNQ系列。能够熟练使用Vivado进行程序的综合和编译。上述描述的任务我可以在短时间内完成，并且让客户完成应用。在项目中已经完成过此类工程的处理，并且在我司产品上成熟应用。