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Help with VHDL-AMS

Bu iş için 17 freelancer ortalamada $198 teklif veriyor

ahmedmohamed85

Dear sir, I have more than 7 years experience in digital design using VHDL please give me more details about the required project

in %bids___i_period_sub_35% gün içinde120%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(322 Değerlendirme)
7.6
zarnescugeorge

Hello! If you have digital design projects I can help you right away! I have 8 years experience in designing digital logic circuits using VHDL and implementing them in FPGA. I was a digital design engineer at Grenoble Daha Fazla

1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(103 Değerlendirme)
6.8
seshupower

Hi, I am a post graduate engineer in VHDL and having very good experience in product design and codding. I will provide you best project to you.

in %bids___i_period_sub_35% gün içinde222%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(55 Değerlendirme)
6.6
GabrielSoare

About what's your problem? I have here a Spartan 3 E board and some knowledge. Cheers Gabriel from [login to view URL]

in %bids___i_period_sub_35% gün içinde300%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(7 Değerlendirme)
4.6
ShaheerJaan

A proposal has not yet been provided

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(20 Değerlendirme)
4.6
alee23

A proposal has not yet been provided

in %bids___i_period_sub_35% gün içinde155%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(11 Değerlendirme)
3.9
botondkirei

Hello! I have experience with describing electro-mechanical systems using mixed signal simulators that can run code written in VHDL-AMS. Looking forward to hear about you. Botond

in %bids___i_period_sub_35% gün içinde150%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(7 Değerlendirme)
4.2
smk55

I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 8 years experience in digital design and well acquainted with ISE, NCverilog, Vivado 2013.4, EDK embedded tools Daha Fazla

in %bids___i_period_sub_35% gün içinde166%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(4 Değerlendirme)
3.4
Fullgrade

For becoming an Academic Freelancer, You need to register Your self as Freelancer while registering with Full Grade. We will ask for your educational background and abilities for which you have applied. You also ne Daha Fazla

in %bids___i_period_sub_35% gün içinde250%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(10 Değerlendirme)
3.8
rameshsundar82

I am Master And Asst prof in Electronics Departmentreputed University from India,I have 15 year exp in this filed. i handled Lot of student projects and guided them.i am strong in digital system VHDL verilog.

1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(1 Yorum)
1.0
salaheldinashraf

A proposal has not yet been provided

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(0 Değerlendirme)
0.0
CSivaRam

With experience of developing more than 18 circuits I will be able to provide help in completing the project

in %bids___i_period_sub_35% gün içinde333%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(0 Değerlendirme)
0.0
madtej

Hi This side Madhur. I am 2+ yrs working professional in digital designing using VHDL. Main area of work is RTL designing. Also has an experience of conducting training to college students in VLSI designing, covering Daha Fazla

in %bids___i_period_sub_35% gün içinde100%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(0 Değerlendirme)
0.0
keyurmahant

I, Keyur Mahant working in One of the leading University of India as Asst. Professor in Electronics and Communication Engg. And Space Technology Center as Project Scientist in which, I am working on “Single Event Upset Daha Fazla

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(0 Değerlendirme)
0.0
wajeehuzzaman

Hi, I am expert in VHDL and can do you project. Please share details with me and we can then discuss it further.

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(1 Yorum)
0.0
jaydeeprangani

I have completed M.Tech. in VLSI and Embedded System. I have completed project on Text Message Entry Design using VHDL.

in %bids___i_period_sub_35% gün içinde200%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(1 Yorum)
0.0
fedemardeguzman

Hi, You can call me Fed (Fedemar). Im an Electronics Engineer with 4 years of experience in Digital Design for both ASIC and FPGA using both verilog and VHDL. Im new here at [login to view URL] but Ive got some experie Daha Fazla

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(0 Değerlendirme)
0.0