DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS
Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero
Bu iş için 11 freelancer ortalamada ₹28737 teklif veriyor
DDR controller core will be generated for selected Xilinx FPGAs as requested in project description. A report will than be generated and simulation results will be shown in ModelSIM. Relevant Skills and Experience Xil Daha Fazla
hello dear!I am interested in your project. Relevant Skills and Experience electronic , control engineering Proposed Milestones ₹27777 INR - finish I can do it well.
DDR SDRAM design verification using standard EDA tool and language.(verilog/system verilog). Relevant Skills and Experience Having more than 6 years industry experience in writing verilog/systemverilog design and DV. Daha Fazla
Dear, We will use xilinx and verilog for coding purposes. We will give RS-232 interface for sending and receiving data to and from FPGA board. Regards, Relevant Skills and Experience 7+ years experience in Rnd Organiz Daha Fazla
I have more than 4 years experience in fpga Ip core development
Please refer to [login to view URL] for our experience/expertise and academic background. We are experts in hardware/software design/development. Relevant Skills and Experience hardware/software design/development. Ex Daha Fazla
I have 10 years of experiences in design and verify using Verilog and SystemVerilog HDL. I have experience of using DE1, DE2 (Altera), Virtex7(Xillinx),.. Please choose me. Best Regards. Relevant Skills and Experience Daha Fazla
D velopement environment xilinx ise and simulation Isim or modelsim. You need to create your own customized ipcore ?