Kapalı

FPGA QAR Project

Bütçe ¥25000-75000 JPY

I have a QAR file that I cannot compile into a POF or PLD file, I would like someone with experience in FPGA to do it. It must be someone with real good knowledge of FPGA.

Beceriler: Elektrik Mühendisliği, Elektronik, FPGA, Mikrodenetleyici, Verilog / VHDL

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İşveren Hakkında:
( 0 değerlendirme ) Japan

Proje NO: #16279694

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Bu iş için 14 freelancer ortalamada ¥52222 teklif veriyor

ahmedmohamed85's Profile Picture
ahmedmohamed85

in %bids___i_period_sub_35% gün içinde55555%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(324 Değerlendirme)
7.7
binyameen441's Profile Picture
binyameen441

Hi There I have checked your project description and understand everything. I am very confident that i can do this project perfectly. Thanks

in %bids___i_period_sub_35% gün içinde38888%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(30 Değerlendirme)
4.7
eopskzs's Profile Picture
eopskzs

in %bids___i_period_sub_35% gün içinde60000%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(2 Değerlendirme)
4.2
rasmeysam's Profile Picture
rasmeysam

Dear hiring manager I really want to know your project requirement. As an electrical engineer I have plenty of experience in FPGA device and verilog/VHDL. I understand your project and it seems like I will do your pro Daha Fazla

in %bids___i_period_sub_35% gün içinde55555%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(5 Değerlendirme)
3.8
olegkaravaev84's Profile Picture
olegkaravaev84

I have more then 10 years of an experience in the FPGA design and mostly with Altera FPGA. I think I can help You. But at first I need to see your project.

in %bids___i_period_sub_35% gün içinde55555%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(3 Değerlendirme)
3.6
lokawiz's Profile Picture
lokawiz

Hi, We would like to understand your project requirement better. We have good RTL and FPGA engineers who may be able to solve the issue with your QAR file compilation. Please review our RTL Hardware IP page at h Daha Fazla

in %bids___i_period_sub_35% gün içinde55555%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(5 Değerlendirme)
3.4
ReconLogic's Profile Picture
ReconLogic

I have in-depth knowledge of altera FPGAs and design software. I can help in figuring out the problem and fixing it.

in %bids___i_period_sub_35% gün içinde27777%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(2 Değerlendirme)
2.8
hayat38402's Profile Picture
hayat38402

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(4 Değerlendirme)
2.6
andreird129's Profile Picture
andreird129

Hello How do you do? I am FPGA expert. I have strong team. I am expert about this field. I will help you. I think i can do it. I want to discuss about your project. I will do my best for your project.

in %bids___i_period_sub_35% gün içinde55555%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(0 Değerlendirme)
3.8
sumbali's Profile Picture
sumbali

I have completed my MS in Electrical Engineering and working in the field of designing for last 3 years. My projects have won more then 10 national level competitions. Area of Expertise -Discrete Time Signal Processing Daha Fazla

in %bids___i_period_sub_35% gün içinde50000%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(0 Değerlendirme)
0.0
writinginvaderz's Profile Picture
writinginvaderz

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(1 Yorum)
0.0
finicky1036's Profile Picture
finicky1036

Hi Sir,, i can convert the file for you in most reasonable price.. for more details you can come inbox with me . you will be pleased working with me. looking forward at you. Best Regards

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(0 Değerlendirme)
0.0
NienYi07's Profile Picture
NienYi07

Hardware developer with extensive verilog development experiences in RTL coding, mapping and place and route in generating a bit stream. Strong in debugging and in getting image to work.

in %bids___i_period_sub_35% gün içinde55555%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(0 Değerlendirme)
0.0
anilch3560's Profile Picture
anilch3560

Hi I have 15+ years of experience in FPGA design & validation. I have worked with many Japanese customers like canon, Kyocera, Ikegami etc. I have worked on both altera & xilinx FPGAs. Relevant Skills and Experience Daha Fazla

in %bids___i_period_sub_35% gün içinde44444%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(0 Değerlendirme)
0.0

Biraz para kazanmak mı istiyorsunuz?

proje Kapalı
Bütçenizi ve Zaman Çerçevenizi Belirleyin
Teklifinizin anahatlarını verin
Çalışmanız için ödeme alın
Kaydolmak ve işlere teklif vermek ücretsizdir