Microprocessor design project using system verilog in Modelsim and physical validation on Quartus Prime. I have started writing code for some of the blocks. The Register file, ALU and Instruction memory are nearly complete. Assistance needed in writing the remainder of the blocks: the instruction register, the micro controller unit, the W register, the program counter and anything else needed to wire everything together. I would also appreciate comments within the design.
Dear sir I have more than 10 years experience in digital system design using system verilog, please message me so that we can discuss Best rgeards
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