Xilinx DDR3 controllers development for Frame buffer (one frame delay)

Kapalı İlan edilme: 6 yıl önce Teslim sırasında ödenir
Kapalı Teslim sırasında ödenir

• Target

DDR3 controllers development for Frame buffer (one frame delay)

• Features

Frame Buffer

input: 1920 x 1080@60 fps, YUV 4:2:2

output: 1920 x 1080@60fps, YUV 4:2:2

• HW Platform

DDR3 controller for Xilinx Zynq-7000 or 7-series FPGA

• Design output

Verilog DDR3 controller source codes, testbench and document

Elektrik Mühendisliği Elektronik FPGA Mikrodenetleyici Verilog / VHDL

Proje NO: #16415806

Proje hakkında

6 teklif Uzak proje Aktif 5 yıl önce

Bu iş için 6 freelancer ortalamada $2185 teklif veriyor

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using fpga please check my profile also please message me so that we can discuss best regards

$2111 USD in 15 gün içinde
(325 Değerlendirme)
7.7
edison4mobile

Hello how are you? I am very interested on your project. I have rich experienced in electronic engineering. In the previous, I have made altera circuit. In that circuit, there are FGPA, CYCLONE, DDR2, RAM, ROM. Al Daha Fazla

$2500 USD in 30 gün içinde
(3 Değerlendirme)
3.2
whitehorsetechn

Greeting, I have understood your Xilinx DDR3 controllers development for Frame buffer task and can do it with your 100% satisfaction. Please ping me for more discussion. I have more than 5 years of experience in Daha Fazla

$2500 USD in 30 gün içinde
(0 Değerlendirme)
0.0