IC layout project for 9-12 months on contract basis
People bidding should be experienced in backend, layout, Cadence Virtuoso, memory compilers
Description : Memory Compiler Engineer to help develop and validate high
performance CMOS SRAM embedded memory compilers.
Will develop compiler modules for CMOS SRAM memories, including physical
tiling, netlist generation, timing analysis and front end model generation.
Should be experienced with circuit design, IC layout, unix scripts, and CAD
verification. Should have at least 2 years experience in memory or IC
design, preferably memory, and at least a Diploma/BS in engineering.
Interested bidders should send their resume along with the bid.
world wide web dot designlabsindia dot com