Lattice ispLSI1032 CPLD Project For Review

Background: I am not a designer or familiar with Lattice’s ispLEVER Classic software, so I would like someone with experience to assist by reviewing my design and help resolve issues I’m experiencing. I have a project that is experiencing what I believe to be timing issues. The project is an 8Meg RAM Card for an Apple IIgs, and there are 2 versions of this computer (ROM1 and ROM3). Both have slightly different timings, but are basically compatible. I currently have a proto PCB I am working with. The project is laid out using Schematic Entry since I have no VHDL knowledge. I have been adding gates and setting net attributes in order to adjust timings in an attempt to achieve a design that works on both versions of the Apple IIgs. I believe if the address and /CAS and /RAS signals could all be latched or clocked, then the design would be stable, however I'm open at all ideas. The project is asynchronous, as I don’t believe there is a set clock that can be used (PHI2), or at least I don’t see a ‘simple’ way to use it, however as mentioned above my skills are rather basic in design. I also don’t have a lot of information about the computer to go on as Apple never made any information public. This video however does cover some of the timings the project deals with: [login to view URL] Related notes from video: When PHI2 high system is in slow mode. 10:55 - Mentioned PHI2 is high extra time because it does a RAM refresh (PHI2 low) then accesses (high). This when CBR Refresh happens. 2 cycles low, then high for 8. 11:40 - Shows PHI2 CBR Refresh pattern. 29:30 - Some DMA notes about fast access possible. 35:30 - More analyzer readings. 39:06 - Shows and talks about DRAM access and CBR Refresh. Project Scope: You will review the project files and look for ways to resolve the timing issues. See attached files for ispLEVER Classic files, and my PCB schematic. If making the project synchronous based on PHI2 or /CCAS is part of the solution, then that’s ok. You can rework the project in any way you see fit. I would prefer to keep the design in Schematic Entry if possible since I do not know VHDL. Anything not listed above will be considered out-of-scope work, and will be compensated separately. Final payment will be made after the project passes testing on several Apple IIgs systems, with several 8Meg RAM Cards, and should not be more than 72 hours after final work has been submitted. I also have several other projects that I would like assistance with. We can discuss those projects separately, and I’m open to working on several projects at once.