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build a 256-line input priority encoder

Bu iş için 16 freelancer ortalamada $26 teklif veriyor

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using vhdl and Verilog, please check my profile also please message me so that we can discuss best regards

1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(366 Değerlendirme)
7.7
1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(149 Değerlendirme)
6.8
EverMaster

Sir, I am an experienced electronics engineer in a leading electronics company. I developed so many Embedded boards, FPGA boards, SoC boards, Microcontroller boards using ORCAD Cadence and written codes in C, VHD Daha Fazla

in %bids___i_period_sub_35% gün içinde100%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(6 Değerlendirme)
4.6
1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(1 Yorum)
3.8
inspiredwhiz

Hello Sir/Ma’am It’s a privilege to know that you are going through my proposal. However, I would like if you can spend a little more time and check my portfolio as well. That’s how you can see what I can do for you Daha Fazla

1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(3 Değerlendirme)
2.2
uptospace2018

Hello sir , i read the requirements , need more details from you , please feel free to contact with us ..

1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(0 Değerlendirme)
0.0
MeddahAbdellah

I will build it in one day in Multisim , I can also write you a VHDL code and run it in ISE. which can be tested on a dedicated chip.

1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(0 Değerlendirme)
0.0
in %bids___i_period_sub_35% gün içinde23%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(0 Değerlendirme)
0.0
sauravsarkar12

I have high experience in verilog coding. I have two research papers on Network on Chip design and cache memories published in IEEE Xplore one of which was presented in Caltech Pasadena. I have work experience as Resea Daha Fazla

1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(0 Değerlendirme)
0.0
1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(0 Değerlendirme)
0.0
SImahoJr

I have the skills needed! If you want simple and efficient (Power and response time) to your design. I am a Msc Student in Electronics Eng, I can do this quickly and efficient. I use proteus software for simulati Daha Fazla

1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(0 Değerlendirme)
0.0
bull3ttrain

I have 7 years of front end design / verification experience working on complex designs. I have worked on 3 generations of on die graphics processors.

1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(0 Değerlendirme)
0.0
AlaBek

I am a computer engineering master student, I have good experience in VHDL and digital electronics design.

in %bids___i_period_sub_35% gün içinde20%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(0 Değerlendirme)
0.0
nikhil9571

I am electronics engineer. I can do this project with your satisfaction. Reach me at 7758011699 or nikhilsabale.9571@gm Relevant Skills and Experience [login to view URL] -vlsi design,verilog,sv, digital design

in %bids___i_period_sub_35% gün içinde35%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(0 Değerlendirme)
0.0
in %bids___i_period_sub_35% gün içinde10%project_currencyDetails_sign_sub_37% %project_currencyDetails_code_sub_38%
(0 Değerlendirme)
0.0
goldduck28

New to freelancer designed a five stage pipelined risc processor so have good knowledge of verilog (HDL)

1 gün içinde %bids___i_sum_sub_32%%project_currencyDetails_sign_sub_33% USD
(0 Değerlendirme)
0.0