Digital VLSI / ASIC Project – Verilog, Synthesis, Gate-Level Simulation & Power Analysis (Cadence) -- 3

@EverMaster

I have around 10 years experience working with xilinx, altera, Synopsys, Cadence tools for FOGA and ASIC design and prototype developments

@anilptk

Hello Hardev, I am a highly skilled Digital VLSI / ASIC engineer with extensive experience in utilizing Cadence tools. I am excited about the opportunity to work on your project, which involves completing an end-to-end RTL-to-power analysis following a standard ASIC front-end flow. With my expertise and attention to detail, I am confident in delivering high-quality results for your project. Regards, anilptk

@peconsultation

Greetings, I can complete a clean end-to-end RTL-to-power analysis flow using Cadence tools with a focus on correctness, traceability, and realistic power numbers. I have hands-on experience with RTL design and verification, synthesis using Genus, gate-level simulation, and power estimation using Joules/Voltus with activity-based analysis. I will structure the flow so each stage is reproducible, document constraints and assumptions clearly, and validate results through waveform and report checks. The deliverables will include synthesized netlists, simulation results, power reports, and a concise explanation of methodology so the work is easy to review or extend. I work efficiently and communicate clearly throughout the process.

@sakshis576

With a diverse background in engineering and technology, I, Sakshi, have had the privilege of working across a range of 3D modeling, architectural design, and even web development projects. These experiences have instilled in me a key set of virtues that I bring to all my work: a commitment to quality, adaptability, and an intimate understanding of designing efficient systems. Drawing from my core skills in Electrical Engineering and my experience with Verilog / VHDL, I am confident in my ability to navigate and complete your Digital VLSI / ASIC Project with ease, meeting the standard ASIC front-end flow you require. I am well-versed in RTL design, synthesis, gate-level simulation – the entire gamut required for this project.

@yanatejaip5s

I have a strong background as an ASIC/RTL Design Engineer. I used to do logic synthesis as well using Cadence Genus and run the GLS (Gate Level Simulation) with and without SDF annotation. Beside that i did some PPA analysis as well based in generated report from TCL script of Genus

@adily1

Hi There, I see you're looking for an experienced Digital VLSI/ASIC engineer for an RTL-to-power analysis project using Cadence tools, which involves a standard ASIC front-end flow. I can help you efficiently navigate this process, ensuring precision at each stage from RTL design to power estimation. My name is Adil Yousuf, and I have over 6 years of experience in Engineering, with expertise in Electronics, Verilog/VHDL, Electrical Engineering, and Very-large-scale integration (VLSI). I am well-versed in utilizing Cadence tools to deliver high-quality results. You can view my portfolio here: https://www.freelancer.com/u/adily1 I am eager to bring my skills to your project and ensure its success. Thank you, Regard, Adil Yousuf

@temciucv

Hello Nate S., We would like to grab this opportunity and will work till you get 100% satisfied with our work. We are an expert team which have many years of experience on Engineering, Electronics, Verilog / VHDL, Electrical Engineering, Very-large-scale integration (VLSI) Lets connect in chat so that We discuss further. Regards

@muhibwatni2

I read your job post and understand that you need a precise RTL-to-Power analysis executed using the Cadence toolchain. I can help by managing the full front-end flow, from synthesis in Genus to gate-level simulation (GLS) in Xcelium, ensuring that your final power estimation in Joules is backed by accurate switching activity. I am proficient in handling standard cell libraries and SDC constraints, ensuring that synthesis is timing-closed before extracting VCD/SAIF files for power analysis. My approach focuses on rigorous data integrity throughout the flow, ensuring that area, timing, and power reports align perfectly with your provided templates and project documentation. I am comfortable working within a structured Cadence environment and can deliver a clean, end-to-end analysis that highlights leakage and dynamic power distribution across your design hierarchy. Regards, WM

@manishSuryaR

Hi, ❤️I’m an experienced Digital VLSI/ASIC engineer with hands-on Cadence flow experience, covering RTL design in Verilog, synthesis, gate-level simulation, and power analysis using provided project templates. ❤️ I will follow a clean, reproducible RTL-to-power flow, ensure correctness at each stage (functional, timing, and power), and deliver clear results aligned with standard ASIC front-end practices. What I will deliver Verified Verilog RTL implementation per specification Successful synthesis using Cadence tools with clean reports Gate-level simulation with matching RTL behavior Power analysis results with documented methodology and outputs Organized project structure and brief explanation of results for review Let’s discuss in chat to proceed further.

@erica351

Hi there, I’m experienced in digital VLSI and ASIC design, having worked on full RTL-to-power analysis projects. With expertise in Cadence tools, I can efficiently complete the front-end flow of RTL design, synthesis, gate-level simulation, and power estimation. I’m familiar with the standard ASIC process and will work efficiently within the provided structure and templates. Looking forward to collaborating on your project. Best regards, Eric.

@kenb452

Hi there, I have strong experience in digital VLSI and ASIC design, specifically with RTL-to-power analysis using Cadence tools. I’m comfortable handling the entire front-end flow, from RTL design to power estimation, following the standard ASIC process. With the provided templates and documentation, I’ll deliver high-quality results on time. I look forward to helping you complete this project. Best regards, Kenneth.

@vtlkanase

Hello, I am an experienced Digital VLSI / ASIC engineer with hands-on expertise in Verilog RTL design, synthesis, gate-level simulation, power analysis, and physical design using Cadence tools. I can deliver: RTL verification / clean Verilog Synthesis using Cadence Genus Gate-level simulation (NCSim ) Power estimation using Cadence Genus Area, timing, and power reports as per provided templates I am familiar with standard ASIC front-end RTL-to-power flow and can follow your project structure and documentation. Ready to start immediately.