Tiny Tapeout Project Submission Help

@Web1devloper

With over 8 years in the tech industry, I bring a versatile range of skills and experience to the VLSI/ASIC domain that's highly applicable to your Tapeout project. Having worked extensively with technologies like Verilog/SystemVerilog, OpenLane, KLayout, and the Tiny Tapeout CLI, I'm well-versed in the entire design flow you're seeking. I can review and optimize your RTL/netlist to meet Tiny Tapeout's exacting limits, build comprehensive yet efficient testbenches, run successful simulations ensuring all automated checks are passed, and adeptly handle packaging your design files and executing a smooth GitHub submission. Aside from my in-depth understanding of ASIC design processes, I also offer proficiencies in Linux, Git, Docker and CI/CD strategies which means that I can provide you with detailed notes on how to easily reproduce the flow for future use or revisions. Additionally, I have had Elaborate experience working with cloud services particularly AWS that will be critical especially as regards hosting or versioning aspects. Lastly, though not directly related to VLSI/ASIC design but adding tremendous value to my profile is blockchain proficiency. In the current era of increasing dependence on cryptocurrencies and NFTs, this skill is gradually gaining popularity given its substantial potential for secure hardware designs.

@WaddahJanajreh93

Hello, I’m an FPGA/RTL and digital hardware engineer with strong experience in Verilog, VHDL, SystemVerilog, simulation, testbench development, synthesis, timing analysis, and GitHub workflows. I also have solid knowledge of the complete RTL-to-GDS flow, including synthesis, floorplanning, placement and routing, STA, DRC, and LVS. My practical exposure to ASIC physical-design tools has been limited mainly by access to commercial EDA software. However, since Tiny Tapeout uses an open-source toolchain, I am comfortable setting up and working with the official OpenLane/OpenROAD flow and GitHub Actions. I can review and adapt the RTL, develop the required testbench, prepare the Tiny Tapeout project files, run the automated checks, generate and package the GDS and supporting files, and provide clear documentation for reproducing the complete flow. I can also support the optional PCB test jig as a separate milestone. I also speak Hebrew fluently, so we can communicate in either Hebrew or English if preferred. Before starting, could you please share the repository and confirm the design complexity, current verification status, target Tiny Tapeout shuttle, and whether the PCB test jig is included in the initial scope? Best regards, Waddah

@naveenc24

Hi, I’m an FPGA/ASIC Design Engineer with hands-on experience in RTL design, Verilog/SystemVerilog, VHDL, simulation, FPGA implementation, and hardware debugging. I also have a strong interest in ASIC/VLSI design flows and can work with a structured RTL-to-submission approach. For your Tiny Tapeout project, I can help with: • RTL design/capture and module integration • Verilog/SystemVerilog implementation • Testbench development and simulation • Functional verification and debugging • Synthesis and design-rule checks • KLayout/GDS-related checks where required • Tiny Tapeout YAML configuration and submission files • Running the Tiny Tapeout CLI flow and resolving submission issues • Final pre-submission verification to avoid last-minute errors I can follow the official Tiny Tapeout flow and adapt to your preferred implementation approach. My focus would be on making the design reproducible, properly verified, and ready for shuttle submission. I’d be happy to review your concept and existing files first, then propose the implementation and verification flow. Regards, Naveen.c

@mobasherreza10

Hi there, While I may not have specific background in VLSI/ASIC, my multi-disciplinary expertise and knack for integrating complex systems makes me the perfect fit for this task. From custom software development to meticulous documentation, I'm accustomed to the meticulous attention to detail your project necessitates. In terms of the specific responsibilities outlined, my proficiency in RTL/netlist design, testbench building, and simulation runs is deep-seated, allowing me to not only address your current project needs but also leave you detailed walk-throughs that guarantee reproducibility for future revisions. My familiarity with a broad array of programming languages and tools including Verilog/SystemVerilog and key platforms like OpenLane, KLayout together with the official Tiny Tapeout CLI ensures your chosen workflow won't be deterred. Best regards, Mobasher Reza