Implement a pipeline MIPS- mini processor in Verlog Many files and modules provided once bidding has commenced As well as a chance for Bonuses
Complete a fully-functional working program in verilog abiding by the following:
1 All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement).
2 The seller will not disclose or divulge in anyway or form any details, acknowledgment of the transaction or deliverables.
3 All of the above and below completed and turned into buyer by 11:00PM EDT 5/4/2004
4 Deliverables must be in ready-to-run condition, as follows:
5 All component verilog files ready to be simulated
5.1 Modules separated into one per file
5.2 Testbench with test case for every command with exception testing were acceptable commands
5.3 Module inter-conductivity diagram
5.4 Write-up detailing your design decisions and any implementation methods, worthwhile describing.
5.5 Simulation logs that show correct operation of the processor. These logs should show the operations that were performed, and then the contents of memory with the correct values in it.
6 The seller will not disclose or divulge in anyway or form any details, acknowledgment of the transaction or deliverables.
7 You have to implement the following ﬁve-stage pipeline:
7.1 IF Instruction Fetch: Access the instruction cache for the instruction to be executed.
7.2 ID Instruction Decode: Decode the instruction and read the operands from the register ﬁle. For branch instructions, calculate the branch target instruction address and compare the registers.
7.3 EX Execute:
7.4 MEM Data Memory Access: Access the data cache for load or store instructions.
7.5 WB Write Back: Write result to register ﬁle.
8 Add the appropriate pipeline registers to your single cycle design. Assume that memory accesses take only one cycle in your implementation.
9.1 arithmetic (unsigned) addu subu addiu
9.2 arithmetic (signed) add sub addi
9.3 logical And Andi Or Ori Xor xori
9.4 shift sll sra srl
9.5 compare Slt Slti Sltu sltiu
9.6 control beq bne blez Bltz J Jr jal
9.7 Memory: Lw Sw Lui Lb Sb
10 All modules should be falling-edge triggered.
11 Handling Hazards you must handle: Keep in mind hazards, so you must be careful that your test programs don’t try to use values too soon after they are generated.
11.1 Data Hazards Data hazards occur when the data produced by an instruction is used as an operand by subsequent instructions.
11.2 Control Hazards Branch instructions present a common case of control hazards. Comply with the MIPS instruction set deﬁnition and implement your processor so that it has one branch delay slot that is always executed regardless of the result of the branch.
11.3 Structural hazards are there any in this design? If so, explain what they are and how you are handling them. If not, why not?
Run on Solaris version of virsim 4.2