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I have designed a custom PCB that picks up a small AC signal (~2V amplitude, 10 ns rise time, 250 ns decay) from a sensor operating on a high-voltage DC bias rail (up to 1500V). The signal is coupled off the HV rail via a capacitor into a three-stage op-amp amplifier. A working reference board exists with the same schematic. My board produces no output and I need an experienced analogue engineer to identify the fault and verify the design. Circuit description HV bias path HV supply (positive, up to 1500V DC) → 10kΩ → 249Ω → signal node B → 1kΩ → sensor. Sensor return at GND. 27nF bypass cap directly across HV supply terminals. Signal current from sensor flows through 1kΩ, developing a voltage pulse at node B. Signal path Node B → 100nF HV-rated coupling cap → node S → 1kΩ to GND. From S into three-stage AD8065 amplifier: Stage 1 inverting (Rf=Rin=1kΩ, Av=−1), Stage 2 non-inverting (Av=+2), Stage 3 non-inverting (Av=+2). Total Av=−4. Output to BNC. Observed symptoms No signal visible at amplifier output when sensor is active With op-amp disconnected, no pulse visible at node S on oscilloscope Adding a 3pF capacitor across Stage 1 feedback resistor causes output to go flat zero — not oscillation, confirmed DC flat on scope A working reference board with identical schematic produces correct output — confirms the design intent is valid Scope of work 1 Review schematic and PCB layout — identify the likely root cause of no signal at node S 2 Advise on methodology to measure and compare stray capacitance at node B between the faulty and working boards 3 Verify the three-stage AD8065 design for stability, bandwidth, and gain — suggest component changes if needed 4 Provide a node-by-node test procedure to systematically isolate the fault 5 Optional: recommend any design improvements for better noise performance or signal integrity
Project ID: 40474690
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Hi there, Since an identical reference board works perfectly, your issue is definitively caused by a physical PCB layout anomaly or an assembly defect rather than a design flaw. A 10ns rise time implies a signal bandwidth of roughly 35MHz. At this frequency, unexpected parasitic capacitance or an incorrect component substitution will easily damp your 2V sensor pulse before it ever reaches the first amplifier stage. My Approach will be: Because the signal vanishes at Node S even with the op-amp completely disconnected, I will immediately audit the PCB layout for proper copper-pour clear-outs. A solid ground plane running directly beneath the high-voltage nodes or the 100nF coupling capacitor can introduce massive stray capacitance, shunting your fast AC pulse directly to ground. I will check if the 100nF HV coupling capacitor populated on the faulty board is suffering from extreme capacitance drop due to DC voltage bias coefficients. This is highly common if a different or lower-grade MLCC dielectric was mistakenly substituted Stray Capacitance Measurement Methodology: I will provide a precise, practical procedure to measure and compare the passive loading at Node B between both boards using high-frequency LCR metering or an RF impedance analyzer setup with low-capacitance active probes to isolate the physical discrepancy. Let’s connect in chat so I can review your schematic and Gerber files to trace this down immediately.
₹15,000 INR in 8 days
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6 freelancers are bidding on average ₹16,333 INR for this job

Signal processing is where embedded systems either deliver or fall apart, and I've been on the right side of that line for over a decade. I've built firmware for products ranging from a smart golf ball tracking 400 Hz IMU data to a sports wearable that needed clean, filtered motion analysis in real time. Those projects taught me exactly how to handle noisy sensor streams and extract meaningful results. I can take your raw data and give you back something you can actually use. I handle the full chain from firmware-level capture through to the processed output, and I don't need handholding along the way. If you need someone who understands both the math and the hardware constraints, let's talk. I'm available immediately and can start delivering from day one.
₹12,500 INR in 2 days
3.3
3.3

Hi, I have analyzed your problem statement and the fact that a working reference board exists points toward a component, layout, or assembly issue rather than a fundamental schematic flaw. Since node S shows nothing even with the op-amp disconnected, the issue likely resides in the high-voltage coupling stage, potentially due to a component failure, a layout discrepancy altering the time constants, or excessive stray capacitance attenuating your fast 10 ns rise-time signal. I will systematically review your schematic and layout, provide a comparative testing procedure to measure stray capacitance against your working board, and verify the stability of the AD8065 stages to isolate and fix the fault. Best regards
₹13,000 INR in 7 days
2.5
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⭐⭐⭐⭐⭐ Senior Analogue Electronics Engineer ⭐⭐⭐⭐⭐ Hello there, I am an analogue electronics engineer specialising in high-voltage signal conditioning circuits, op-amp stability analysis, and PCB fault diagnosis. No signal at node S with the op-amp disconnected points to a problem upstream of the amplifier entirely. The coupling capacitor, the 1kΩ load to ground, or node B itself is the fault location — not the AD8065 stages. The 3pF feedback cap causing DC flat output is a separate stability concern worth addressing, but it's secondary to finding why node S shows nothing. The most likely root causes in order of probability: the 100nF coupling capacitor is faulty or incorrectly placed, a PCB trace to node S has a solder bridge or open via, the 1kΩ load resistor at S is missing or wrong value, or stray capacitance on the HV node B is attenuating the 10ns rise time pulse before it reaches the coupling cap. My approach: DC voltage verification at node B first, then impedance comparison between working and faulty boards at node B and S using an LCR meter or VNA to quantify stray capacitance differences, then systematic coupling cap verification. For the AD8065 three-stage design — 10ns rise time signals require careful attention to PCB parasitics and power supply decoupling at each stage. Can you share the schematic and PCB layout files so I can identify the specific fault location before advising on the test procedure?
₹25,000 INR in 7 days
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AD8065 expert. Node S capacitance fault. I'll find it. HV analog signal chains are my specialty I have hands-on experience designing and debugging high-voltage analog signal chains, including capacitively coupled front-ends and precision op-amp amplifiers. Your symptom — no signal at node S with the op-amp disconnected — points strongly to a passive component fault or excessive stray capacitance at node B killing the signal before it even reaches the amplifier. The 3pF feedback cap causing a flat DC output is also a classic sign of layout-induced parasitic issues rather than a schematic error, which aligns perfectly with the fact that your reference board works fine on the same schematic. I will systematically review your PCB layout against the reference board, compare stray capacitance at node B using a precision LCR meter methodology, verify the three-stage AD8065 design for gain-bandwidth stability with your 10ns rise time requirement, and deliver a prioritized node-by-node test procedure so you can isolate the fault efficiently. I can also suggest layout and component improvements for better noise floor and signal integrity on the HV rail. I am confident we can get your board producing clean output. Happy to start immediately.
₹20,000 INR in 7 days
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