you are required to design a multiplier system that operates based on "Booth encoding" sequential.
the multiplier has two 3 bit input, data1 & data2, and one 6 bit output called [login to view URL] following are the main input/output signals associated with multiplie unit:
1- input consist of the following signals
Start A 1-bit control signal to incluse the start of the multiplication process. its assume that data1 and data2 are valid beforw asserting the start signal.
Data1 A 3bit value represting a signed multipliend given in 2's complement represtation
Data2 A 3bit value represting the multiplier given in 2's complment represtation.
2- Output consist of the follwing signals
-Ready A 1 bit signal indicating the completion of the multiplication process.
-DataOut A 6 bi value that represents the result of performing the mu;tiplication (i.e. product). this value is only valid when Ready signal is asserted.
Dear sir
I have more than 8 years experience in digital design using Altera quartus2 please check my profile also please message me so that we can discuss
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Hi,
I had done MS in Digital System Design. Also I had several years of experience in FPGA, Altera Quartus, VHDL and Verilog HDL. Also I had worked on Booth multipliers. I can do this project for you.
Kind Regards,
I am familiar with Verilog and VHDL and I will do the project for you in one week. We will be in touch so that you meet you requirements for the project.