There are two signals, A and Z. During a certain period, Z will always be low, and go high only once. Between any two Z pulses, there will be x A pulses. The purpose of this project is to determine the number of A pulses and the 'even-ness' of the A pulses; whether they're of uniform length during both high as well as low phase; the average high-to-low and low-to-high timings of each A pulse must be determined. This data must be then transferred via serial communication to a PC (using RS485). It is perfectly acceptable to dump raw data to the PC and do all the processing on the PC itself. The average frequency of the A signal will be range between 10 and 50 Khz. The frequency of Z is the same, in the sense of how long Z will remain 'high' before falling back to 0, but it will pulse only once per cycle. Z can be seen as a delimiter indicating the start of each cycle; the data to be collected is for the A signal for the duration of a single such cycle.
9 freelancers are bidding on average ₹25863 for this job
Will provide complete design with simulation result Relevant Skills and Experience Verilog, FPGA, RS232, RS485 Proposed Milestones ₹27777 INR - milestone How much time you needed it in.