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Design and test a VHDL model for the instruction cache of a speculative out of order VLIW processor.

Design and test a VHDL model for the instruction cache of a speculative out-of-order VLIW processor. Your VHDL code should have the following:

- PC register updated on falling_edge of the clk to one of the following values: PC + VLIW_INST_SIZE, branch_target_PC, or EXCEPTION_ROUTINE_PC. PC register should be initialized to 1000 Hex when reset is active. Assume that the project ISA requires EXCEPTION_ROUTINE_PC to be F000 Hex.

-8K byte direct map instruction cache for fetching one VLIW word, which is equivalent to four micro-instructions, every cycle. The input PC for a read cycle to the ICache comes from the PC register above, and the write PC is an input to the architecture that you should name Imiss_PC.

Submit one file that shows your complete and clearly commented VHDL code and waveform diagram from a benchmark simulation that shows that your code correctly write and read instructions from the ICache and generates correct hit/miss signal.

Design and test a VHDL model for the front end cluster of a speculative out-of-order VLIW processor. Assume the ISA specification provided in Moodle. Your VHDL code of the front end cluster should have the following:

1. Three components: instruction cache, BTB, and register renaming.

Plus any control logic you may need implemented as dataflow code.

2 Pipeline staging registers, updated on falling edge of clks. You can use process for these.

3. Two pipeline stages: First stage to include instruction cache and BTB. Second stage to include decode logic, logic to allocate entries in buffers for instructions (reorder buffer, reservation stations, load buffer, store buffer) and register renaming table. When any instruction buffer is almost full (has less than 4 microinstruction, the allocation logic should assert a stall signal back to the fetch stage pipeline to stop fetching more instructions.

4. BTB should be 4K entry direct map branch target buffer with bimodal predictor. It need to have one read port accessed to perform branch prediction using instruction fetch PC. It also should have one read-modify-write port to update the BTB using executed branch PC to update an entry, whenever a branch executes. For both ports, you can ignore the least significant three bits of the branch PC, since branches are aligned within the 8 byte VLIW instruction stored in the instruction cache block.

5. Register renaming table in the Rename pipeline stage: this renames registers using the reorder buffer as physical register file. Sample code file of rename table is posted for you to understand, then modify and use for this project.

6. Reorder buffer size, reservation stations buffer size, load buffer size and store buffer size should ne 32, 32, 16, 16 entries respectively. Assume that all are circular circular buffers with head and tail pointer registers.

Beceriler: Verilog / VHDL

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( 3 değerlendirme ) Beirut, Lebanon

Proje NO: #15726113

3 freelancers are bidding on average $361 for this job

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using VHDL, please check my profile also please message me so that we can discuss

in 10 gün içinde500$ USD
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atharbaig6167

hi there, I'm Embedded systems Engineer with four years of experience of verilog and VHDL. I read your description and i'm sure i can complete it within your required time. Price can be negotiated. . Relevant Skills Daha fazlası

in 10 gün içinde250$ USD
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masov2017

Hello, I have read your article carefully and I convinced that I can finish your project. I am an electrical engineer and expert in logic circuit design. I have done several VHDL projects here. Relevant Skills and Exp Daha fazlası

in 3 gün içinde333$ USD
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