I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog).
I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result.
I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND implementation. However a more complex example is much more appreciated.
Please no blinking LED already present in the Intel Website.
I might have future works based on how we go with this.
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Hi I have worked on the altera tools and FPGAs and also have used de nano and de-2 115 boards and quartus software. I can make an example design and can explain you very well. Thanks
Highly interested with your project and I'm ready to start right now. My completion rate is always 100% that I STRICTLY BITE ONLY WHICH I CAN CHEW. Please message me to discuss more!
Design Engineer with Experience in Large scale complex projects development with practicing in Verilog, VHDL, SystemVerilog and programming with C, C++, Python. Let's discuss further.