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Recursive karatsuba multiplier (16bit)

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mastor31

Hi, I am good in VHDL and Verilog. I implemented ip core of floating multiplication, FIR filter in HDL. I am extensive experience in ISE, Vivado of Xilinx and Quartus of Altera. Please elaborate your requirement to p Daha Fazla

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(9 Değerlendirme)
4.1

Bu iş için 6 freelancer ortalamada ₹12472 teklif veriyor

ahmedmohamed85

A proposal has not yet been provided

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7.6
SANGITAR

I have proficiency with VHDL and Verilog. I am good with Xilinx and Altera FPGA. Are you referring any IEEE paper

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4.1
olegkaravaev84

I have more than 10 years of an experience in the FPGA/ASIC design and also I have an experience in the implementation of a mathematical algorithms.

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(3 Değerlendirme)
3.6
yemelitc

Hello, This is a rather tricky project, so I raised the reward. Any particular reason for that algorithm on just a 16bit signed integer? But anyway as a Verilog HDL programmer and one who knows the algorithm, I can Daha Fazla

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1.9
lokawiz

Hi, We will build your verilog multiplayer using Karatsuba algorithm. We have very good verilog RTL development expertise. Please let us know a good time to discuss your requirement so we can provide you with the so Daha Fazla

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