I need a verilog code for recursive karatsuba multiplier for 16bit signed integers.
Hi, I am good in VHDL and Verilog. I implemented ip core of floating multiplication, FIR filter in HDL. I am extensive experience in ISE, Vivado of Xilinx and Quartus of Altera. Please elaborate your requirement to p Daha Fazla
6 freelancers are bidding on average ₹12472 for this job
I have proficiency with VHDL and Verilog. I am good with Xilinx and Altera FPGA. Are you referring any IEEE paper
I have more than 10 years of an experience in the FPGA/ASIC design and also I have an experience in the implementation of a mathematical algorithms.
Hello, This is a rather tricky project, so I raised the reward. Any particular reason for that algorithm on just a 16bit signed integer? But anyway as a Verilog HDL programmer and one who knows the algorithm, I can Daha Fazla
Hi, We will build your verilog multiplayer using Karatsuba algorithm. We have very good verilog RTL development expertise. Please let us know a good time to discuss your requirement so we can provide you with the so Daha Fazla