A rather simple SystemC project (cosisting of 14 cpp files of the size similar to the one accessible at [url removed, login to view] ) is to be converted into synthesizable VHDL (ISE 10.1 project). The conversion can be done manually or automatically (using an adequate EDA tool), the only requirement is that the code has to comile and synthesize on the ISE.
I can pay for the task up to 125 USD.
12 freelancer bu iş için ortalamada 113$ teklif veriyor
Hi, I have been working in VLSI design for 14 years. I have worked in RTL design and verification in SystemC,Verilog and VHDL. I can complete this job easily. Thanks, Amit designlabsindia dot com
we in to ASIC and FPGA design working for different soc design. We have exp in VHDL , verilog, SVA, systemc , C++ we have more than 5 yrs exp in ASIC and FPGA design and synthesis