A rather simple SystemC project (cosisting of 14 cpp files of the size similar to the one accessible at [url removed, login to view] ) is to be converted into synthesizable VHDL (ISE 10.1 project). The conversion can be done manually or automatically (using an adequate EDA tool), the only requirement is that the code has to comile and synthesize on the ISE.
I can pay for the task up to 125 USD.
CPP files would be converted individually into VHDL files in five days. Files would then integrated and compile and synthesized during next two days. One day is left for any unforeseen errors or stuck up scenarios. Emp Daha Fazla
12 freelancers are bidding on average $113 for this job
Hi, I can do this for you. HIGH QUALITY guaranteed. Please check PM for details.
Hi, I have been working in VLSI design for 14 years. I have worked in RTL design and verification in SystemC,Verilog and VHDL. I can complete this job easily. Thanks, Amit designlabsindia dot com
we in to ASIC and FPGA design working for different soc design. We have exp in VHDL , verilog, SVA, systemc , C++ we have more than 5 yrs exp in ASIC and FPGA design and synthesis
We have expertise into systemC,VHDL, Verilog, FPGA board developed.
We can help with this project. We have good experience with System C and VHDL using Mentor and Xilinx Tools.
I have worked in Verilog/System C for over 10 years. And I can deliver this project in 14 days.
Hello! I will do the conversion manually. If you know the language some of the comments are in (according to google translate, polish), for example: //Posrednie wyniki, dla kazdej z metod predykcji, then I may ask Daha Fazla
I am an expert in High Level Synthesis. I have tools to perform System C to Verilog. ISE can take verilog for synthesis if you need verilog let me know I can provide you with it. Will need to talk to you. Skype: ajay. Daha Fazla