Kapalı

VHDL expert needed

Design a serial communication protocol i.e., telegram containing data bus, address bus, read/write bus and checksum(CRC).

1. read/write access is to be transferred. If CPU is doing a write access, then it should have 1 byte address and 1 byte data and control bits if possible.

2. Read bus should read the address to be transferred.

3. The write bus should transfer the PSS signal or the chip select signal for the peripheral boards.

4. PSS is of 16 bits and the status of PSS signal should also be transferred.

5. The data should be on write access for front transfer and on read access for reverse transfer.

6. Define the type of telegram as read or write type.

7. Checksum should check if the data is valid or not.

Beceriler: Verilog / VHDL, Elektronik, Elektrik Mühendisliği, Mikrodenetleyici, FPGA

Daha fazlasını gör: http startup kpi ua sc2015 design startup images logo 3 2 png, build php did_dest 84768&r1 1&r2 2&r3 3&r4 4&hour 0&repeat 3&gid 17&t 0&option 256, build php did_dest 84768&r1 1&r2 2&r3 3&r4 4&hour 0&repeat 3&gid 17&t 0&option 256did_dest, plugin developers demand a better security release process after wordpress 4.2 3 breaks thousands of websites wordpress tavern w, wordpress customization - expert needed - read scope and apply, design website 2-3 days, Upgrade Moodle from 2.0.4 to Moodle 3.2, 2. Architecture diagram. 3. User Interface Wireframe or the frontend design. 4. data flow design / ER diagrams if any, guideline 4.2.2 - design - minimum functionality, macro expert 4.2 crack, guideline 4.2.6 - design - commercialized templates and app generation services, arcgis 10.3 assignment 4-2, how to remove checkout step 2, step 3, step 4 in opencart, oracle vm manager 3.4.2 installation, salesforce for outlook 3.4.2 download, 1,8,2=4 3,8,4=6 2,9,3=6 4,9,3=12 6,7,3=?, directions write read rewrite. repeat steps 2 and 3 as needed summary, read the numbers and decide what the next number should be. 8 4 2 6 3 2 4, directions: write, read, rewrite repeat steps 2 and 3 as needed summary

İşveren Hakkında:
( 0 değerlendirme ) Santa Clara, United States

Proje NO: #28995468

Bu iş için 8 freelancer ortalamada $221 teklif veriyor

(471 Değerlendirme)
8.0
(90 Değerlendirme)
6.8
umg536

Hi there, I'm bidding on your project "VHDL expert needed" Being a professional electrical engineer, I can do this project for you. please leave a message on my chat so we can discuss the budget and deadline of the pr Daha Fazla

$250 USD in 6 gün içinde
(8 Değerlendirme)
5.6
doggar302

Hi! I am an Electronic engineer, PCB Layout, Circuit Design, microcontroller, STM32 microcontroller, C programming expert having past experiences with ,Altium, arduino, pic, AVR, chipkit and Texas instruments microcont Daha Fazla

$250 USD in 7 gün içinde
(16 Değerlendirme)
5.4
Lightcanon

Hello, I am digital design engineer with +5 years of experience in VHDL/Verilog. I have worked on a serial protocol which is similar to yours (has address bits, embeds synchronization bits and CRC16 bits to the stream, Daha Fazla

$95 USD in 4 gün içinde
(53 Değerlendirme)
5.6
(40 Değerlendirme)
5.1
randuwa

Hello.. I am holding masters degree in electrical engineering.. I have very good experience in vhdl and verilog.. I have gone through your requirements and I am sure that I can do this project perfectly.. Kindly drop m Daha Fazla

$200 USD in 4 gün içinde
(12 Değerlendirme)
3.7
taamouchabdelhak

Hi, there I am a VHDL and FPGA expert, I can complete your project perfectly and provide live explanation. Contact me to discuss more

$250 USD in 7 gün içinde
(9 Değerlendirme)
3.4