Hi I have a VHDL project which synthesizes, but it has some simple errors when simulating (unconnected signals mainly).
I need someone who can fix it and run a simulation to identify one issue.
Bu iş için 13 freelancer ortalamada $24 teklif veriyor
A FPGA/IC design expert with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise: FPGA, Daha Fazla
Electronics Engineer with experience in Verilog, SystemVerilog, and Programming Firmware, C, C++. Reply me more project details to discuss further. Regards.
I am interested in your project. Is it possible to discuss the project details? If you can provide information about the details, we can proceed faster. what program do you use quartus or something else
hi, i have experince in understnading other person codes and fixing issues with verilog and VHDL. i will be able to do this in a matter on minutes. i have expertise in verilog and VHDL. i will be using Xylinx produ Daha Fazla
Hello! I can help you for your problem! I have 5 years experience whith practice vhdl. It is my first work in this platfotm. I hope it will be successfully! Thanks
Hi, I have 3 years experience and worked on complex hardware projects and create module from the scratch. Hope to help you on the issue