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Vivado simulation using LVDS interface

This project need to implement the several LVDS interface between Xinix Atix and a sensor buffer

This project is completed after simulating transfer (Buffer content ==> FPGA RAM content)

This is the testing project, so that, you can get more projects after completing this.

If you have experiences, you can complete within a few days.

Deliverables: Verilog & buffer frame communication simulation in Xilinx Vivado

Beceriler: Verilog / VHDL

Daha fazlasını gör: xilinx xapp1324, xilinx hdio, vivado clock_delay_group, lvds source synchronous ddr deserialization, xilinx lvds ip, ddr lvds, xilinx idelay example, xilinx buf_in, using delphi command asp project, project need unique company name, customer simulation using queue java, template interface multimedia project macromedia flash, web project need money, using dall bll asp project, starting online project need someone host, using user interface setup project, project simulation using promodel, java project file system simulation using fat, project code network simulation using, In this project, you will be implementing a rail road yard simulation program. The user will provide a set of incoming cars, and

İşveren Hakkında:
( 3 değerlendirme ) Dandong, China

Proje NO: #18985392

Seçilen:

rakendr7

Hello, I've experience in multiple Xilinx FPGA based project which involves ADC/Sensor captures. I've experience in simulation using Xilinx simulator as well as Modelsim. I've done similar projects with putting sensor Daha Fazla

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1.0

Bu iş için 6 freelancer ortalamada $379 teklif veriyor

ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Daha Fazla

$500 USD in 10 gün içinde
(75 Değerlendirme)
6.2
RKY18

Hello. After reading over your project this looks like a perfect fit for my skill sets. I have 10+ years of FPGA/CPLD and Verilog/VHDL experience. I have finished many Altera FPGA designs on [login to view URL] recently. Daha Fazla

$400 USD in 10 gün içinde
(5 Değerlendirme)
4.6
thasleemkamila

I have well experienced in doing such kind of jobs...................................................................................................................................................................

$200 USD in 5 gün içinde
(10 Değerlendirme)
4.3
ZhenExpert

Hello, I am very interested to work in this project because it is good fit for me. I have experiences with Vivado and Vivado HLS. and also i have full exp with FPGA as EE engineer. I can handle your project and will Daha Fazla

$400 USD in 7 gün içinde
(0 Değerlendirme)
0.0
sohailnagra

Hi, i am having expertise in Vivado, Xilinx ISE. I have experience on working with different Fpga Boards. I can also share my sample work if required. After referring my skill set you will find me best candidate for th Daha Fazla

$388 USD in 8 gün içinde
(0 Değerlendirme)
0.0