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VHDL for Pipelined MIPS Processor

The pipelined processor is divided into four units: the controller, datapath, instruction memory and data memory [url removed, login to view] task in this part will be to (1) design the controller unit, (2) design the instruction memory and data memory, (3) design datapath units, (4) put all 4 units together to form the pipelined MIPS processor, and (5) work out two test programs for the processor as a whole.

It should take a maximum of 8 hours to be completed in 1 week. I will upload detailed instructions once the freelancer agrees to work on it.

Beceriler: Elektronik, Verilog / VHDL

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İşveren Hakkında:
( 0 değerlendirme ) United States

Proje NO: #4439565

1 freelancer is bidding on average $35 for this job


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