The FPGA project is to porting a WLAN’s PHY cores into a Xilinx FPGA development board (E.g Spartan 3A). Use of the public domain WLAN’s PHY cores from Rice University’s WARP project ([url removed, login to view]), the cores (Matlab Simulink’s mdl files) porting into a Xilinx FPGA development board. We recommend to goto the [url removed, login to view] link (above), download the matlab files, and try out yourself first before your bid.
Details Project Tasks are followings;
• Break the WARP’s Simulink’s mdl files into transmitter (Tx) and receiver (Rx) parts (currently, the WARP mdl files are combined) because the core logics are too big for the Spartan3A chip, and port the each part into a Xilinx’s Spartan3A-DSP board.
• Perform a slight modification and adding for the WARP mdl files to fit the board and demonstration (will be discussed later).
• The Xilinx’s Spartan3A-DSP board is combined with a P160 Analog-to-Digital daughter card (ADC/DAC) by Avnet. The WARP Simulink mdl and P160 ADC Simulink mdl files are need to integrate together for TX and RX.
• A simple Matlab GUI will design for configure and run the board.
Qualifications for this project;
• Must familiar with Xilinx FPGA design tools including System Generator, and required experience for porting/debug on various Xilinx development boards.
• Must familiar with Matlab and Simulink
• Must familiar with WLAN technology (OFDM modulation/demodulation), DSP
• Experience on DSO, Spectrum analyzer, ADC/DAC board, hands-on digital signal processing, and data analysis.
If you are interested to submit this project, we encourage to download the WARP project and try first before you bid. And submit precise technical details that how you can divide the cores into TX/RX. And expect to have multiple technical discussions before we finalize the project contract.
Bu iş için 16 freelancer ortalamada $2003 teklif veriyor
hi i am ready to this project, if you want more information we can chat here
I am professional matlab programer: [url removed, login to view]
I am automation domain expert ( see profile), and I am supported by two electronics engineers with 20 years of experience. I have seen the reffered site and downloaded the required materuial.Discus. Regards, Brajesh
Experienced Digital Design Engineer, please check PM.
I have over 10 years experience in FPGA design. I can deliver the project on time. But before start a success FPGA porting, we must clarify sevearl key questions. 1, Please speicfy which FPGA develop broad is target. Daha Fazla
I propose that trying to port the WARP HDL code to the spartan 3 series is a waste of time as there is no PPC CPU in these FPGAs. The outcome can be delivered by delivering a SOC 'system on chip' solution that pretty m Daha Fazla
Hi, I'd done few of projects on xilinix FPGA's and CPLD's. I have experience on DSP and VLSI. let me know your queries for clarification.
i have ported DSP adaptive algorithm on vertex 5, designed using simulink ported on fpga using system generator, similar to project.
Hi I am an electrical engineer have good hands in Matlab & Verilog, Plz see the personal message.
HI, I have 7+ years experience in FPGA design activities. Do contact me if you are interested with my bidding. My Mail: vlsi dot solution at [url removed, login to view]
My skill set involves Verilog , VHDL with 36 months experience. I am familiar with the internal working of SPARTAN generation FPGAs. I have implemented control logic for IO transition board in Mission Computer to be fi Daha Fazla
I can do this, but to do it right would require two months of work. 320 hours at $60/hr = $19,200 I am still most interested in this project.