EXPLORE

Electronics Engineering Matlab and Mathematica Mobile App Development Verilog / VHDL
Profile cover photo
User Avatar

Dhruva P.

@dhruva1705

0.0
0

0.0

0.0

0%

Hardware Engineer

$20 USD / Hour

Flag of

India (10:55 AM)

Joined on July 7, 2012

$20 USD / Hour

I have done engineering in Electronics and Telecommunication and Masters in Microelectronics VLSI and Display Technology. My LinkDin Profile - [login to view URL]

Reviews
0 Reviews

No reviews to see here!

Experience

Hardware Engineer and Investor.

Jul, 2011 - Sep, 2017

6 years, 2 months

Working experience in SPARC processor development.

Jul, 2011 - Sep, 2017

6 years, 2 months

Worked on SAT level functional verification of - # Coherency Ordering Unit : Used to maintain inter / intra node cash coherency in the multi CPU systems. # Coherency Sub System : It consists of mainly multiple level 3 cashes with coherency ordering unit . # RAIL Interface network : It is the interface network between the Level-2 and Level-3 caches in the CPU. Skills Required - Systemverilog & UVM.

Jul, 2011 - Sep, 2017

6 years, 2 months

Education

Indian Institute of Technology, Kanpur

2009 - 2011

2 years

M.Tech (Electrical Engineering)

Flag of

India

2009 - 2011

2 years

Qualifications

National Cyber Olympiad

2001

Awarded for the Distinctive performance in the 1st National Cyber Olympiad held on 23rd oct 2001 at more than 700 centres in india and gulf.

2001

robotics competition

2007

IIT Kgp

Secured 16th place out of 200 robots in the robotics competition step climber held in IITKgp in 2007.

2007

National Science Olympiad

2001

Distinctive performance in the 3rd National Science Olympiad held on 29th jan 2001.

2001

Verifications

Registered Users

Total Jobs Posted

Freelancer ® is a registered Trademark of Freelancer Technology Pty Limited (ACN 142 189 759)

Copyright © 2026 Freelancer Technology Pty Limited (ACN 142 189 759)