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Digital Design Electronics Verilog / VHDL
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Dragisa S.

@hdlveca

4.6
9

4.0

4.0

100%

ASIC Design Verification Engineer

$10 USD / Hour

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Serbia (5:43 AM)

Joined on November 3, 2008

$10 USD / Hour

I have been working for veriest types of IP Core Development in Verilog/VHDL. Build Verification environments in eLanguage (Specman) and System Verilog with UVM.

4.6 · 9 Reviews
Reviews
Y

Translate VHDL files to Verilog $80 USD

Thank you for the brilliant work :) Great! Very friendly, and nice person to deal with. Definitely know what he has to do.very good communication. definitely would hire again.

Former Client (inactive)

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A

VHDL assignments $85 USD

Rating: 4.0/5.0

Mohammed Abdul Khaled S.

@ak450ece2009

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, Denmark

16 years ago

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M

GPS stabilized oscillator $85 USD

Rating: 2.5/5.0

Michel B.

@michelbelanger

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, Canada

16 years ago

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F

Bonus for hdlveca on 9/4/2009 6:21:24 PM $45 USD

Rating: 5.0/5.0

Stephen B.

@fpgavw

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Central District, Hong Kong

16 years ago

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Instant bonus for hdlveca (from bid request id 1,080,241) on 8/2/2009 3:57:52 AM $99 USD

Rating: 5.0/5.0

Stephen B.

@fpgavw

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Central District, Hong Kong

16 years ago

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Certifications

F

Foundation vWorker Member

Verifications

On time

100%

On budget

100%

Accept rate

100%

Repeat hire rate

11%

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