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Module LeadDec 2007 - Feb 2011 (3 years)
1.) FLIR IR Camera for FLIR System Works done for FLIR IR Camera projects during the onsite assignment in Sweden: • Timing closure for Vega, Sirius and Mira FPGAs used for various FLIR IR cameras. • Verification of SDRAM/DDR Controller IP. • Verification of various components of Vega, Sirius and Mira projects. 2.) DVDR Wipro GE Health Care (A joint venture with General Electric and Wipro): FPGA development for Digital DVD Recorder used for the ultrasound scanner. The Cyclone III FPGA i
Senior EngineerJul 2006 - Dec 2007 (1 year)
4.) D/AVE 3D IP CORE(Video IP) The display accelerator and vector engine is a display core IP which can be used in either FPGA or ASIC which is developed by TES Germany. Major task for this project includes optimization for resource utilization, pipelining of the architecture to meet the required timing and RTL coding of various modules and timing closure. The entire design supports 125 MHz. Responsibilities: Low Level Design and Resource Optimization of the Design. Pipelining of the Architecture
Design EngineerAug 2005 - Mar 2006 (7 months)
7.) TCP/IP ipv6 HARDWARE ENGINE. Description: The project is to develop FPGA based hardware engine for the TCP/IP protocol. Responsibilities include coding and testing of the LINK LAYER, ICMP and PING Handler modules of the project. Responsibilities: Design concepts. RTL coding using VHDL. Documentation. Environment: Team Size : 8 Tools : Xilinx [login to view URL] Device : VIRTEX-4. Client : SAMSUNG KOREA.
Front End Hardware DesignerOct 2004 - Aug 2005 (10 months)
8.) FPGA based Spring Testing Machine. Description: The micro controller based board controls the operation of the spring testing machine. The onboard fpga incorporates Direction Discriminator, UART, Timer, FIFO, ROM and Keyboard interfacing. The controller utilizes these different functionalities in the fpga for the operation of the testing machine. Responsibilities: Design concepts. RTL coding using VHDL. Testing. Documentation. Environment: Team Size : 2 Tools : ALTERA Qu
IC Design Front EndAug 2002 - Sep 2004 (2 years)
9. ) micro controller mc 80c51. 10.) Generic Pipelined Frequency Synthesizer. 11.) Correlator (64 bit) for PCM Data Acquisition System. 12.) uart. 13.) Frame Synchronizer for PCM Data Acquisition System.
BTech in Electronics and Communication1992 - 1996 (4 years)
VLSI Design (2002)PARK Controls and Communication Pvt Ltd, Bangalore
One-year course and training in VLSI design from Park Controls and Communication (2001 August to 2002 July).