Education
2005–2008 ENSERG ( School of Microelectronics Engineering, Grenoble - France), Master’s degree of Scientific and Executive Engineering. Major : Microelectronics, Computer Science and Nanotechnologies.
2003–2005 IPEST (Preparatory School of Science and Technology, Tunisia), a specific 2 year undergraduate program leading to a very competitive national examination to the French engineering Schools “Grandes Ecoles”, specializing in mathematics and physics.
2002-2003 Scientific Baccalaureate, Mathematics Major, Highest Honors, Lycee Ibn Rachiq, Ezzahra, Tunisia.
PROFESSIONAL EXPERIENCES
08/13 – now Mission for STMicroelectronics (Grenoble)
Subsystem and Top level Verification Engineer EASII-IC
Confidential Chip : Multimedia SoC for Gameplay
- Subsystem Verification based on UVM methodology of Video Subsystem.
- Development of integration tests for both Video Subsystem and DMA.
- SW update and delivery of HW patches for RTL integration team.
Technical Environment :
UVM, NCsim, QuestaSim, SVN, VHDL, Verilog, SystemVerilog, C, Perl.
10/12 – 07/13 Mission for STEricsson (Grenoble)
(10 months) Top level Verification Engineer EASII-IC
Confidential Chip : Multimedia SoC and integrated LTE for Smartphones ST-ERICSSON
- Development of integration and functional tests for USB3 Subsystem.
- Improving TB structure and USB VIPs optimization.
Technical Environment :
QuestaSim, Clearcase, VHDL, Verilog, C.
06/12 – 09/12 EASII-IC (Grenoble)
Verification Team Leader
Confidential Chip : 3Mpixel Imager for Nokia mobile phones
- Define global verification plan and implementing new tests.
- Functional verification according to SMIA++ standard (Nokia)
- Run and debug tests for RTL/Gates/DFT/FPGA
- Modeling analog blocs and mixed simulation.
- Management of the verification team (5 engineers).
Technical Environment :
NCsim, Synchronicity, VHDL, Verilog.
07/11 – Now Mission for STEricsson (Grenoble-France)
(4 months) Digital Verification Engineer – Technical Leader EASII-IC
Confidential Chip : System-on-Chip for Smartphone 4G ST-ERICSSON - FPGA prototyping
- Chip compilation and elaboration. Adapt IPs for FPGA prototyping constraints.
- Booting the chip and debugging the list of regression.
- Giving feedbacks on design and improving the Hardware/Software quality.
- Technical management and reporting.
Technical Environment :
QuestaSim, Clearcase, VHDL, Verilog, C.
01/11 –06/11 Mission for STEricsson (Grenoble-France)
(4 months) Functional Verification Engineer EASII-IC
Chip 9600 : System-on-Chip for Smartphone 4G ST-ERICSSON - FPGA prototying
- Developing integration's verification tests for IPs SPI, UART, Muti-Timers, IrDA and IRRC.
- Participation in development of generic and modular verilog Test bench.
- Supporting verification teams on new project using Tester USB 2.0 OTG.
Technical Environment :
QuestaSim, NCsim, Clearcase, VHDL, Verilog, C.
04/10 –12/10 Mission for STEricsson (Grenoble-France)
(9 months) Functional Verification Engineer EASII-IC
Confidential Chip : System-on-Chip for mobile phone 4G ST-ERICSSON
- Development of integration tests for ARM Cortex A11, USB, DMA, UART and Memories Controllers FSMC
- Improving Test bench structure and Verification IP generation flow.
- Setting a new verification specification of new IP USB 2.0 OTG.
- Development a new verilog Denali USB tester and software for booting USB IP.
- Supporting integration team to solve RTL bugs and validate hardware patches.
Technical Environment :
QuestaSim, NCsim, Clearcase, VHDL, Verilog, C.
08/08 – 03/10 Mission for STMicroelectronics (Grenoble-France)
(19 months) Top Level Verification Engineer EASII-IC
Confidential Chip : System-on-Chip for 4G Communication Keys ST-ERICSSON
- Development and update of functional and integration tests for IPs Coresight, AXI bus, Memory controller ARM PL35x, Security bloc HAM and Fuses.
- Hardware/Software bug tracking.
- Supporting both Integration and Timing Analysis Teams to produce specific tests.
- Testbench update.
- Gate-level debug for Coresight IPs
Technical Environment :
QuestaSim, Clearcase, Eclipse, VHDL, Verilog.
02/08 – 06/08 STMicroelectronics (Grenoble-France)
(5 months) Engineer Graduate Internship
Confidential Chip : Smart TV Core (1.4M Gates)
ARM9, Dual-Core Architecture
- Specification of Transactional Level Modeling (TLM) verification IPs.
- Implementing of two new TLM verification IPs : UART and I²C.
- Improving of a new platform of regression by implementing sequential and parallel test runner.
- Validation of a new internal verification tool of "non-regression"
Technical Environment :
VHDL, SystemC, NCSim, PERL, Tck/Tk.
06/07 - 09/07 Selecom (Perpignan-France)
(4 months) Engineer Internship - FPGA prototyping.
WIMAX Repeater 802.16 : chip for 4G communication
- Definition of a new product of 4G repeaters.
- Technical specification of the chip and requirements for digital IP signal processing.
- Prototyping and characterization of the circuit using FPGA Cyclone II.
Technical Environment :
QuartusII, ADS.
TECHNICAL SKILLS
Languages : Verilog, VHDL, SystemC, language C/C++, assembler, Java.
Scripting : Shell, Perl, Tcl.
EDA MicroElectronics : “Front-End” Logic Synthesis Leonardo (Mentor Graphics)
Logic Simulation NCSim ( Cadence )
Modelsim Mentor Graphics
Altium Designer Altium
EDA FPGA : ISE design tools Xilinx
QuartusII Altera
FPGA Platform : CycloneII (Altera)
Protocols : Bus AMBA (APB, AXI, and AHB), I2C, USB, RS232.
System On Chip : Processor ARM9, ARM11, Cortex-A15.
Versioning : Clearcase (Rational Software), Synchronicity.
LANGUAGES
English : Fluent ( TOEIC score : 780/990)
French : Excellent
Arabic : Mother tongue
INTEREST / ACTIVITIES
- 2006 : Founder and Chairman of ATUGE Grenoble association until Mai 2008.
- Amateur developer on FPGA and ATMEL microcontrollers.
- Solar energy system researcher.
