srvedula adlı kullanıcının profil görüntüsü
@srvedula
India bayrağı Hyderabad, India
31 Mart 2006 den beri üye
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srvedula

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Vedula V SitaRam Email: TECHNICAL SUMMARY * 11 years of experience in ASIC/VLSI/Verification/Testing/Design involving ASICs, Models, Microprocessors, SoCs. * Underwent Verisity Specman training and Synopsys DC training. * Cisco CCNA certified. Preparing for CCNP. * Experienced in test plan development, environment development, test cases implementation, models development, regression, random testing and coverage. * Verification Experience in Hyper Transport Tunnel/Cave, Controller Area Network (CAN), USB 1.1, PCI, AGP, I2C, DMA, SDRAM/SRAM/FLASH, Sparc Processor. * Verilog, System Verilog, V2K, VPI, Vera, Specman, Test builder. * VCS, Verilog-XL, Specview, Vericov, Covermeter. Cisco Systems, Inc. Apr05-Sep05 * Contracted at Cisco. Verified HT block. Verified FRCPU DMA Engine. Synopsys Inc, Hyderabad, India Jul04 -Mar05 (Sr Engineer, R&d) * Verified System Verilog, NTB, VPI. Satyam Computer Services Ltd., Bangalore, India Jun03 - Jul04 (Senior System Analyst) * Designed Micro controller I/F for PDIUSBD12 to bridge CAN and USB. * Wrote CAN monitor. Developed test plan and environment. Tested on FPGA. Designed CAN/RS232 Bridge. * Verified HT Tunnel and Cave in forward direction. Wrote test plan and test cases. Assisted testing on FPGA. * CAVLC IP core: This project aims to develop CAVLC (Context adaptive variable length code) of H.264. JM reference model is used for test stream generation and the streams are sent via serial interface . LSI Logic Inc., Milpitas, CA. Oct01 - Mar03 (Senior Design Engineer) Verification of USB 1.1 Host * Managed the entire verification related activity for USB 1.1. Integrated bus functional models with the system environment. * Prepared test plan, arranged reviews. * Wrote several test cases and ran test vectors in Verilog and VERA * Maintained Clock Controller Logic test cases. CMOS Chips Inc., Santa Clara, CA. Mar99 - Oct03 (Senior Design Engineer) (Contracted at Synopsys, HAL, Ishoni Networks, Toshiba and NEC). Synopsys Inc. (6 Months): Ran benchmark designs on VCS 6.1 Pre Alpha. HAL (17 Months) * Wrote scripts to automate the random generator running process on system model. * Ran the random test generator to generate many test cases and debugged failures. * Wrote targeted corner test cases for I/D cache debug registers. * Updated and maintained I/D cache MMU test cases. ISHONI NETWORKS INC. (3 Months) * Wrote test plan for SDRAM/SRAM/FLASH Memory controller and memory arbiter. * Wrote several tests in standalone (Verilog) and System (Mips assembly). * Verified the Memory controller and memory arbiter using Verilog and VERA * Found several bugs and fixed them TOSHIBA INC. (5 Months) * Wrote test plans for DMA and I2C modules * Wrote test vectors in MIPS and VERA to verify the DMA controller and I2C * Wrote I2C behavioural model and monitor in Verilog for verification. NEC ELECTRONIS INC. (3 Months) * Led a team of 4 verification engineers to verify BlueNile ASIC. * Complete verification of Blue Nile chip that includes development of testplan & test vectors. VERA language was used to write the test suites * Development of complete system level concurrent transaction involving PCI, CPU Bus, SDRAM & DMA transactions with many random techniques in VERA * Found many bugs & also fixed them along with designer * Found many spec related issues & reported them for spec update * Developed DMA Controller test plan and test cases in VERA. * Ran coverage for complete chip in Vericov. * Developed corner case tests by analysing the coverage results. Led a team of 4 verification engineers to verify BlueNile ASIC. * Developed DMA Controller test plan and test cases. Ran coverage for complete chip in Vericov. RCUBE TECHNOLOGIES INC. Oct97 - Mar99 Senior Design Engineer (Contracted at Chromatic Research and Indus) Chromatic Research Inc., (9 Months) and Indus Inc., (6 Months) * Developed test plans for PCI Target, DMU (DMA Monitoring Unit) and SPDIF Controller. * Developed AGP Monitor and transaction generator. Tested PCI Master/Target Models, AGP Core. HCL Technologies Sep95 - Aug97 * Designed CFG/CSR logic, I2C Bus interface, Synchronization logic for PCI target. * Developed SBA(Side Band Address) Logic, Q-logic and Target-Host interface in AGP Master simulation Model. * Wrote diagnostics for a LAN-WAN interface card. Education: ME in ECE. Personal: Green Card Holder. 1 of 2
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