tnrajaraman adlı kullanıcının profil görüntüsü
@tnrajaraman
Singapore bayrağı Singapore, Singapore
5 Kasım 2012 den beri üye
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tnrajaraman

Çevrimiçi Çevrimdışı
More than 16 years of industrial experience in Front end FPGA/VLSI Design using Verilog/VHDL. Currently doing Freelance consulting.
$55 USD/hr
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Tecrübe

Senior Engineer

Nov 2009

RTL Design and coding Bus Functional model design and coding Test plan, execution and Bug fixes. Top level Verification plan and execution. Micro architecture System level Debugging FPGA Synthesis

Technical consultant

Jul 2009 - Nov 2009 (4 months)

RTL Design and coding Bus Functional model design and coding

Senior Engineer

Feb 2006 - Jul 2009 (3 years)

RTL Design and coding Bus Functional model design and coding Test plan, execution and Bug fixes. Top level Verification plan and execution. Micro architecture System level Debugging FPGA Synthesis Porting part of Chip into Tharas box for Faster simulation Metal ECO fix wire length calculation and Design changes.

Design Engineer

May 2001 - Feb 2006 (4 years)

RTL Design and coding Bus functional model design and coding Test case writing and execution Board design and bring up

Eğitim

B.E.(E.C.E)

1997 - 2001 (4 years)

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