I would like to create a real-time lane detection using Zynq-7000 board uing VHDL and C programming languages. This project should have 3 milestone updates. and it is due on Monday April 13th 2020. [URL'yi görüntülemek için giriş yapın]
...for modeling the system as an FSM (finite-state-machine). Specify in the Sketch same sketch the meaning of each state, the input(s) and output(s). 2) Design the FSM using Verilog code and simulate the FSM. (Use comments to indicate the meaning of each variable.) 3) Write a report to explain in detail the state diagram, FSM design source code, and simulation
Attached I have my simulation of a 32-bit RISC pipelined processor (picture also attached), and I have a few errors in the code that won't let it compile. I am trying to find someone to simply aide in the debugging process so I can continue my work, I am hoping it would be done in the next day or two.
I implemented the system that is attached in the picture, but when it came time to c...few errors. I want someone to help troubleshoot said errors, and then help create an assembly language program to MUL two 32-bit numbers to make a 64-bit answer within the Verilog environment to prove out the initial system. Shouldn't be complicated I'm just stuck.
Need someone that is deeply knowledgeable in verilog programming. Need to be ABLE to build the CPU, build memory-less, combinational components and sequential components (i.e create mux and adder's in ALU), implement 2 stage pipeline for RISC-V Processor, etc.
I want to make the interface between the sinewave function generator and FPGA kit via ADC that belong to the same kit 1. Show the result on the test - bench window 2.I Want to show the practical result on LCD screen 3. Also use the leds to show the digital value for analog value
I need to test a structural model of a sequence detector using t flip flops. I know my t equations, I have my entity and the testbench I am using to test the model. I need help constructing the structural model. It is based off a behavioral and dataflow model I already created. The software I'm using is Aldec.