write a Verilog description for the Program Counter (PC) and Register File (RF) components of a MIPS CPU.
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Program Counter – program_counter.v
The program counter maintains the current 32-bit instruction address and outputs it on the “pc” bus The program counter
is a synchronous unit that is updated at the rising edge of the clock signal “clk”. The program counter is asynchronously
cleared (zeroed) whenever the active-high reset signal “rst” is asserted. The value of the program counter is updated based
on the value of the 4-bit “pc_control” signal. See Table 1 for description of the update behavior. If the program counter is to
be updated by a Jump Immediate instruction then the 26-bit “jump_address” bus contains the value that should be used to
compute the new pc value. For Jump Register instructions the 32-bit “reg_address” bus contains the new PC value. If the
program counter is to be updated by a Branch instruction then the 16-bit “branch_offset” bus contains the value that should
be used to compute the new pc value.
Table 1 pc_control[3:0] encoding and description
pc_control Updated PC Value Description
4’b0000 PC = PC + 4
PC is updated to the next sequential instruction
address.
Figure 1) Block diagram of a MIPS CPU. In this assignment you will create the Program Counter (PC), Register File (RF), and
Arithmetic Logic Unit (ALU).
Overview
In this assignment you will write a Verilog description for several components of a MIPS CPU. You will
create the Program Counter (PC), Register File (RF), and Arithmetic Logic Unit (ALU).
Modules
The following sections describe each module that you must implement in this assignment.
Program Counter – program_counter.v
The program counter maintains the current 32-bit instruction address and outputs it on the “pc” bus.
The program counter is a synchronous unit that is updated at the rising edge of the clock signal “clk”.
The program counter is asynchronously cleared (zeroed) whenever the active-high reset signal “rst” is
asserted. The value of the program counter is updated based on the value of the 4-bit “pc_control” signal.
See Table 1 for description of the update behavior. If the program counter is to be updated by a Jump
Immediate instruction then the 26-bit “jump_address” bus contains the value that should be used to
compute the new pc value. For Jump Register instructions the 32-bit “reg_address” bus contains the
new PC value. If the program counter is to be updated by a Branch instruction then the 16-bit
“branch_offset” bus contains the value that should be used to compute the new pc value.
Table 1) pc_control[3:0] encoding and description
pc_control Updated PC Value Description
4’b0000 PC = PC + 4 PC is updated to the next sequential instruction
address.
Program Counter jump_address [25:0] pc_control [3:0]
pc[31:0]
clk
rst
clk
rst branch_offset[15:0] reg_address[31:0]
Register File
raddr0[4:0]
raddr1[4:0]
waddr[4:0]
wdata[31:0]
wren
rdata0[31:0]
rdata1[31:0]
clk Arithmetic Logic Unit
operand1[31:0]
control[3:0]
result[31:0]
overflow
operand0[31:0]
zero
Data Memory
addr[31:0]
wdata[31:0]
wren[3:0]
rdata[31:0]
clk 0 1 0 1 0 1
Instruction Memory
address[9:0] instruction[31:0]
Sign Extension
in[15:0] out[31:0]
Control Unit
reg_file_rmux_select
reg_file_dmux_select
instruction[31:0]
data_mem_wren[3:0]
pc_control[2:0]
reg_file_wren
alu_mux_select
alu_control
alu_zero
instruction[25:21]
instruction[20:16]
instruction[15:11]
instruction[15:0] instruction[25:0] instruction[15:0]
instruction[31:0]4’b0001 PC = {PC[31:28] , (jump_address*4)[27:0]}
When the CPU executes an unconditional Jump
instruction the new 32-bit PC is the concatenation of
the upper 4-bits of PC and the 28-bit result of the jump
address multiplied by 4. See definition of the Jump
instruction (opcode 2).
4’b0010 PC = register
PC is updated with the value contained in the register
specified in the instruction. “reg_address” holds the
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